Topic
Aliasing (computing)
About: Aliasing (computing) is a research topic. Over the lifetime, 1887 publications have been published within this topic receiving 34821 citations.
Papers published on a yearly basis
Papers
1 Jan 1994
TL;DR: The procedure of adaptive slicing from the exact representation of the part model is described, which will improve part accuracy and minimize building time especially for the parts with highly curved surfaces.
Abstract: The Solid Freeform Fabrication (SFF) process significantly reduces part specific setup manufacturing lead time. This process has been primarily used in fabricating prototypes for design visualization and verification. However, the major impact of this process on the future of manufacturing technology would be the possibility of fabricating functional parts for end use. One of the obstacles to this goal is the insufficient accuracy of the final physical part produced by the process. From the software point of view, the major sources of the inaccuracy come from the inappropriate data transfer format and the 3D aliasing' or Stair-stepping' problem. The '3D aliasing' problem can be reduced by adapting the layer thickness to the geometry of the part. In this paper, the procedure of adaptive slicing from the exact representation of the part model is described. This will improve part accuracy and minimize building time especially for the parts with highly curved surfaces. The procedures are implemented and a comparison to the conventional uniform layer thickness method will be discussed.
83 citations
Patent•
20 Dec 1990TL;DR: In this article, an aliasing logic (100) in an instruction decoder allows indirect access to a source or destination register specified by the operands of the macro-code instruction or the opcode of macro-instruction while executing a sequence of microinstructions.
Abstract: An aliasing logic (100) in an instruction decoder. If a complex microinstruction flow is in progress, it operands can be accessed through alias registers (116). This allows indirect access to a source or destination register specified by the operands of the macrocode instruction or the opcode of the macroinstruction while executing a sequence of microinstructions. These aliased operands are maintained by the macroinstruction aliasing logic (100) in the register (116). The instruction decoder issues new instructions by driving a machine bus (110) with the correct information during each clock cycle. Mousetrap multiplexer (104) chooses between several sources of opcode and operand fields and routes the them to the machine bus (110) through several translation stages and multiplexers.
82 citations
TL;DR: In this article, the aliasing conditions of shifted-Fresnel diffraction with fast Fourier transform (FFT) have been investigated, and the effect of aliasing error in a short propagation distance has been investigated.
Abstract: Numerical simulation of Fresnel diffraction with fast Fourier transform (FFT) is widely used in optics, especially computer holography. Fresnel diffraction with FFT cannot set different sampling rates between source and destination planes, while shifted-Fresnel diffraction can set different rates. However, an aliasing error may be incurred in shifted-Fresnel diffraction in a short propagation distance, and the aliasing conditions have not been investigated. In this paper, we investigate the aliasing conditions of shifted-Fresnel diffraction and improve its properties based on the conditions.
82 citations
TL;DR: It is shown that significant improvements can be obtained by using two signature analyzers instead of one and the weight distribution of a class of codes of arbitrary length is given.
Abstract: Single and multiple multiple-input-signature-register (MISR) aliasing probability expressions are presented for arbitrary test lengths. A framework, based on algebraic codes, is developed for the analysis and synthesis of MISR-based test response compressors for BIST. This framework is used to develop closed-form expressions for the aliasing probability of MISR for arbitrary test length. An error model, based on q-ary symmetric channel, is proposed using more realistic assumptions. Results are presented that provide the weight distributions for q-ary codes (q=2/sup m/, where the circuit under test has m outputs). These results are used to compute the aliasing probability for the MISR compression technique for arbitrary test lengths. This result is extended to compression using two different MISRs. It is shown that significant improvements can be obtained by using two signature analyzers instead of one. The weight distribution of a class of codes of arbitrary length is also given. >
81 citations
TL;DR: The purpose of this study is to explore in depth the most common problem present in images, the aliasing, or more generally speaking, the sampling problem, and imply a specific approach in the hidden surface determination, the introduction of a variation of the already used A-buffer or Z-buffers, as well as an extensive study of the filtering problem.
81 citations
Related Topics (5)
Performance Metrics
| Year | Papers |
|---|---|
| 2021 | 71 |
| 2020 | 57 |
| 2019 | 74 |
| 2018 | 59 |
| 2017 | 50 |
| 2016 | 74 |