Abstract: An aliasing logic (100) in an instruction decoder. If a complex microinstruction flow is in progress, it operands can be accessed through alias registers (116). This allows indirect access to a source or destination register specified by the operands of the macrocode instruction or the opcode of the macroinstruction while executing a sequence of microinstructions. These aliased operands are maintained by the macroinstruction aliasing logic (100) in the register (116). The instruction decoder issues new instructions by driving a machine bus (110) with the correct information during each clock cycle. Mousetrap multiplexer (104) chooses between several sources of opcode and operand fields and routes the them to the machine bus (110) through several translation stages and multiplexers.

Abstract: Single and multiple multiple-input-signature-register (MISR) aliasing probability expressions are presented for arbitrary test lengths. A framework, based on algebraic codes, is developed for the analysis and synthesis of MISR-based test response compressors for BIST. This framework is used to develop closed-form expressions for the aliasing probability of MISR for arbitrary test length. An error model, based on q-ary symmetric channel, is proposed using more realistic assumptions. Results are presented that provide the weight distributions for q-ary codes (q=2/sup m/, where the circuit under test has m outputs). These results are used to compute the aliasing probability for the MISR compression technique for arbitrary test lengths. This result is extended to compression using two different MISRs. It is shown that significant improvements can be obtained by using two signature analyzers instead of one. The weight distribution of a class of codes of arbitrary length is also given. >

Abstract: An investigation of the properties of multiple input shift registers for signature analysis is presented. The assumption of independent errors at the register inputs has been used to model the register behavior as a Markov process whose equations have been solved to obtain the exact dependence of aliasing probabilities as a function of test length, input error probabilities, and feedback structure. Some unique featured of maximum-length registers are proven. Accurate simplified expressions of aliasing probability are derived for use as tools in the evaluation of the coverage. >

Abstract: The aliasing probabilities of multiple-input signature registers (MISR) with m inputs for a 2/sup m/-ary symmetric channel, where each of the (2/sup m/-1) possible errors is equally likely, are analyzed. For this error model, the aliasing probabilities of MISRs are analyzed using the weight distributions of maximum-distance-separable (MDS) codes. The results show that the aliasing probabilities over the 2/sup m/-ary symmetric channel do not depend on the polynomials that characterize the MISRs. That is, for the 2/sup m/-ary symmetric channel, the aliasing probability of an MISR based on a primitive polynomial is exactly the same as one based on a nonprimitive one. In addition, it is observed that the aliasing probabilities, P/sub al/ (n), as a function of test length n, are monotonous for error probabilities p=0.2, 0.4, and 0.8. The aliasing probabilities of multiple MISRs based on Reed-Solomon codes are analyzed again for the 2/sup m/-ary symmetric channel, using the weight distributions of Reed-Solomon codes, which are MDS codes. >

Abstract: We are now going to abstract the Call and Return primitives. Let (g, r) be the current abstract stack. We use the following notations: g = ~ P , c , h , ~ , ~ / r = {(gi, ui)}iEl , , = r(g) E ~ ~ [ . ] The abstract store v = v[p] thus corresponds to the current generalized control point g, and p is the set of locations accessible to procedure P. In order to deal with the locations created during procedure calls, we will use the function A +t,_,u + : SVal [p-] --+ S--V-~[# +] which takes and abstract store defined o v e r / t and inserts the new locations in #+ / ~ with undefined values. The function At,_~-#,+ does the same but assigns the value of the location ~ to the new locations. On the opposite, the function A~+,u_ : SVal [it+] ~ SVal[p-] forgets every information about the locations in #+ # . A formal definition is given below. Def in i t i on 16 For any sets # C_ it +, let T(I~ +) be an upper approzimation of the lattice "P(Iz + --* SVal) , a ± and 7 ± being the abstraction and meaning functions. The functions A + A"+,u_, and A ~ " u + are defined by: ~x+ (P ) = ,~+({, , e (it+ ~ SVal) : % e : ( e ) } ) / t d.t+ A~+,,,_(p) = a-({%,:a E ,,/+(e)}) zX~-#,+ (P) = a+({oE (~+ --, SVal): %,e "t-(P) ^V2~+ E (it+ / t ) : a(,~+) = a(.~-)}) 7 . 1 P r o c e d u r e c a l l s Let us call {g', r ~} the abstract stack after the procedure call. The generalized control point g~ = (P ~, c~, h ~, g~, ~ ) is easily determined using the formal parameter binding function II, and the environment ~. We call # ' the set of locations accessible to P~. We have # ' = #sUpvUPAUPL,~ ~ ~ ' where P3 = #$ contains the locations shared between procedure P and procedure P~, namely the locations accessible to plo (for pl° < p by construction), and t i #v , PA and p~ are the locations that are local to Pt and respectively belong to Value, Alias and Local. The second element r ~ is defined by: r' = p,,(r[/g, ~/ / /g," / ] U {/g', v'/}) The first abstract store ~ is what remains of the abstract store v after the call to procedure P~. Remember that all the shared locations in #$ must be "erased" to be consistent with our abstraction ~. This is achieved through the use of A ~ , ~ , where PH = P -PS is the set of "hidden" locations of procedure P.

Abstract: This paper deals with the aliasing probability of multiple-input data compressors used in self-testing networks. It is shown that a far more general class of linear machines than linear feedback shift registers can be used for data compression purposes. The function of these machines is modeled by a Markov process. The steady-state value of the aliasing probability is shown to be the same as for single-input signature analysis registers. An easily verifiable criterion is given that allows one to decide whether a given linear machine falls into this class of multiple-input data compressors. The steady-state value of the aliasing probability is shown to be independent of the correlation of the data streams at the inputs of the data compressor. Two kinds of circuits are analyzed in more detail with respect to their aliasing properties: linear feedback shift registers with multiple inputs, and linear cellular automata. Simulation results show the effect of the next-state function on the steady-state value of the aliasing probability and the effect of correlation on the transient response.

Abstract: Mach; UNIX/OSF; HP-PA; virtually addressed cache architecture; PA-RISC; virtual memory Mach shares memory between tasks by virtual address aliasing. This means a physical page can be mapped to more than one virtual page at a time. This works well on hardware architectures that use a physically addressed cache, but can cause some problems for architectures that use a virtually addressed cache resulting in less than best possible performance. This memo describes four experiments that were tried to improve the performance of Mach running on a machine with a virtually addressed cache. The experiments were implemented and measured against a collection of benchmarks. The measurements were then compared to those taken on a "base" implementation of Mach on the same hardware to get a clear idea of the performance benefit of each experiment.

Abstract: A compression technique, called periodic quotient compression, which eliminates the problem of aliasing is presented. The compression in signature analysis is based on polynomial division, where the remainder is the signature and the quotient is discarded. With this technique one looks at both the remainder and the quotient and assumes that the good circuit response is known a-priory during the design of the linear feedback shift register (LFSR). The concept of periodic polynomials is used to completely characterize the quotient, thus eliminating aliasing. The maximum number of bits required to compress an N-b response to achieve zero aliasing is determined. The authors provide an algorithm for constructing an LFSR to achieve this bound for any given circuit under test. >

Abstract: The production of computer-generated video presents a number of difficulties not encountered with motion pictures. Interlaced scanning and the color subcarrier of NTSC video are responsible for special problems such as interline flicker, and chroma aliasing. As in motion pictures, temporal aliasing is also an issue. A renderer can sample and filter a moving image in an arbitrary manner and is not constrained to simply imitate the behavior of a television camera. This paper explores several different spatiotemporal antialiasing filters and how they affect the quality of video animation.

Abstract: Design techniques that can improve the aliasing probabilities of signature circuits for VLSI BIST (built-in self-test) are presented. The proposed techniques are based on the binary weight distributions of error-correcting codes over GF(2) and GF(2/sup m/). The technique considered for calculating the aliasing probability of signature circuits is appropriate for a vector supercomputer. Some of the calculations were done using the S810 supercomputer. The vectorization ratio of the program was 99.885% for an MISR (multiple-input signature register) with 16 inputs and for test length n=100-105. >

Abstract: A method and apparatus for eliminating aliasing in an electronic still camera without the use of a birefringent filter is disclosed. Instead of a birefringent filter, mechanical dithering is utilized to move the pixel elements of a solid-state imager in a controlled manner with respect to an incident image. The movement of the pixel elements by mechanical dithering spreads light from the incident image among neighboring pixels of the image sensor and therefore performs the same function as a birefringent filter to prevent aliasing in an electronic camera.

Abstract: The probability of a fault-free signature has been calculated in the above-named paper (see ibid., vol.C-35, no.9, p.830-7 (1986)) and in an earlier paper by the same author (see ibid., vol.C-29, no.7, p.668-73 (1980)). Implicitly, it was considered as the probability of masking due to signature analysis. It is shown here that this does not correspond exactly to the probability of aliasing. A new definition is given. The difference centers on the event where there are no bit errors in the data to be compressed. When the response of the circuit is correct, the signature is fault-free. However, there is no aliasing. >

Abstract: We present a compositional definition of the order of evaluation of variables in a lazy first-order functional language. Unlike other published work, our analysis applies to all evaluation strategies which may use strictness information to change the normal (lazy) order of evaluation. At the same time it can be adapted to pure lazy evaluation yielding a sharper analysis in this case. It can also be adapted to take advantage of any information about the order in which primitive functions evaluate their arguments. The time complexity of the method is that of strictness analysis.We also present a compositional definition of the set of variables which denote locations where the result of an expression might be stored. This analysis yields a simple solution to the aliasing problem.Using these two analyses we develop a new algorithm for the destructive update problem.

Abstract: In the mid-1970s, 3-D marine survey design was primarily constrained by the ability to locate the position of the boat and streamer. Line spacings were, therefore, typically greater than 100 m. (Even if the navigation technology had been more accurate, it is likely that denser grids would not have been acquired because of the cost. This new method, 3-D, carried a price tag that was often considered uncomfortably high for a technology that was as yet unproven.) To minimize crossline aliasing effects, it was most prudent to record data in the dip direction.

Abstract: The authors have designed a family of parallel dataflow analysis algorithms for execution on a message-passing MIMD (multiple instruction multiple data) architecture, based on general purpose, hybrid dataflow analysis algorithms. They have exploited the natural task partitioning of the hybrid algorithms and have explored a static mapping-dynamic scheduling strategy. Alternative mapping-scheduling choices and refinements of the flow graph condensation utilized are discussed. This parallel hybrid algorithm family is illustrated on the reaching definitions problem, although parallel algorithms also exist for many interprocedural (e.g., aliasing) and intraprocedural (e.g., available expressions) problems.

Abstract: We present a static analysis method for determining aliasing and lifetime of dynamically allocated data in lexically scoped, higher-order, strict and polymorphic languages with first class continuations The goal is validate program transformations that introduce imperative constructs such as destructive updatings, stack allocations and explicit deallocations in order to reduce the run-time memory management overhead Our method is based on an operational model of higher order functional programs from which we construct statically computable abstractions using the abstract interpretation framework Our method provides a solution to a problem left open [Hudak 86]: determining isolation of data in the case of higher order languages with structured data

Abstract: Aliasing estimations for cellular automata (CA) and linear feedback shift registers (LFSR) data compactors are presented. As data compaction is a heavily relied on technique for built-in self-test (BIST) the results should be of practical, as well as theoretical interest. Aliasing estimation techniques for multiple-input data compactors are considered. In particular, exact and approximate computation techniques are developed and discussed for CA and LFSR registers. Aliasing estimates for CA and LFSR structures are provided for the ISCAS-85 benchmark circuits for single stuck-at and single delay faults. >

Abstract: A Hopfield network has been proposed as a novel approach to achieve memory associativity and to solve combinatorial optimization problems. The authors presently relate optimization problems to problems of memory association of a Hopfield network and show the limitations of the network when it is used to solve NP-complete problems from the viewpoints of the aliasing effect among pattern sets and the information capacity embedded in such a network. A simplest Hopfield network for solving the race traffic problem is constructed to manifest the similarity between memory association and optimization problem resolution as well as to discuss the stability of convergence in synchronous and asynchronous operation modes. By transforming the traveling salesman problem to a memory association problem, it is shown that the use of a Hopfield network for solving NP-complete problems is, in fact, overloaded

Abstract: Operation decomposition proof obligations are given for a language with blocks and unrestricted procedure calls with reference parameters and global variables. Post-conditions of the initial and final states of the computation are used; existing proof rules are for post-conditions which are predicates of the final state only. Aliasing, as arising from reference parameters, and static scoping are dealt with in the Hoare-like proof system by the use of a “syntactic environment”.

Abstract: A system is presented which is capable of performing perspective spatial transformations at video rate, by means of a mapping function which can vary at frame rate. The mapping is implemented by two successive applications of a one-dimensional algorithm operating in scan-line order, using a framestore to store an intermediate image. A novel one-dimensional filtering algorithm provides a continuous mapping from source to destination co-ordinates, significantly reducing aliasing. Emphasis is placed on the design of a novel stream processing architecture which, coupled with an efficient pipelined co-ordinate generation system, provides single-cycle per output pixel performance.

Abstract: In Computer Graphics, aliasing occurs by the reconstruction of a continuous image starting from a set of discrete samples. Most anti-aliasing algorithms give best results in conjunction with a scan-line algorithm. Algorithms for anti–aliasing objects using a Z-buffer were believed to be difficult.

Abstract: This paper addresses the problems of aliasing as associated with frequency response analysis. Modern composite frequency response analysers rely on the use of digital memory and digital-to-analogue techniques for the storage and generation of their test waveforms. The application of such techniques, however, results in reconstituted waveforms which are non-band-limited in the frequency domain. If these waveforms are applied directly to the system under test then the system output cannot be guaranteed to be digitally sampled without introducing aliasing effects into the measurement process. The basis for a technique for compensating for the effects of aliasing in such frequency response analysers is presented. This technique is largely based upon a software algorithm, and removes the need for anti-aliasing filters.< >

Abstract: The author discusses the design of pre- and post-filters for a system where down-sampling (decimation) is followed by up-sampling (interpolation). This is called a decimation-interpolation system. Some important properties of decimation-interpolation systems are discussed. A theoretical result is presented where necessary and sufficient conditions are given to eliminate frequency aliasing. Based on this theoretical result, an iterative two-step joint pre- and post-filter design algorithm is presented which implicitly suppresses aliasing. Characteristics of the design method are discussed along with some examples. >

Abstract: A Linear Feedback Shift Register (LFSR) can be used to compress test response data as a Signature Analyzer (SA). Parallel Signature Analyzers (PSAs) implemented as multiple input LFSRs are faster and require less hard ware overhead than Serial Signature Analyzers (SSAs) for compacting test response data for Built-In Self-Test (BIST) in IC or board-testing environments. However, the SAs are prone to aliasing errors because of some specific types of error patterns. An alias is a faulty output signature that is identical to the fault-free signature. A penetrating analysis of detecting capability of SAs depends strongly on mathematical manipulations, instead of being aware of some special cases or examples. In addition, the analysis should not be restricted to a particular structure of LFSR, but be appropriate for various structures of LFSRs. This paper presents necessary and sufficient conditions for aliasing errors based on a complete mathematical description of various types of Sas. An LFSR reconfiguration scheme is suggested which will prevent any allasing double errors. Such a prevention cannot be obtained by any extension of an LFSR.

Abstract: The recent interest in one-dimensional linear hybrid cel- lular automata (CA) raised two outstanding questions, both of which are answered in this paper: how to construct a general linear hybrid cellular automata such that it has a maximum length cycle, and how the aliasing properties of such automata compare with linear feedback shift registers, when used as signature analyzers. This is accomplished by formally demonstrating the isomorphism which binds this kind of cellular automata to the linear feedback shift registers. Consequently these cellular automata can be analyzed as linear machines; linear al- gebraic techniques are applied appropriately for the transformations; and a useful search algorithm is developed which, given an irreducible characteristic polynomial, finds a corresponding linear hybrid cellular automata. Such cellular automata are tabulated for all irreducible and primitive polynomials up to degree 16, plus a selection of others of higher degree. In the initial research of (6), some new questions were raised, as the study of CA by themselves has been rather empirical, with extensive simulations having been per- formed to analyze their behavior in detail (14). In partic- ular, it is important to determine when a CA' is capable of generating an exhaustive set of patterns (excluding the all 0's pattern), and thus is said to have a maximum length cycle. In 1141, a variety of CA are examined and lists of their cycle structure are obtained by computer simulation. In (6), some conjectures have been made as to the nec- essary and sufficient conditions to build a CA with a max- imum length cycle. The solution to this first open problem is presented here. Moreover, in the context of digital circuit testing, LFSR's have been used as very effective signature ana- lyzers. Given the better randomness properties of CA as pattern generators, the question can be asked whether they extend to become better signature analyzers, when used in a similar fashion to LFSR's within methods of data compaction. Some initial research on the aliasing properties of CA from a probabilistic modeling is intro- duced in (7). The answer to this second question is pre- sented here, through an algebraic analysis of the struc- tures.

Abstract: A signature analysis technique which analyzes the aliasing probabilities of multi-input signature registers (MISRs) is presented. An error model is developed on the assumption that in each time slot error symbols occur uniformly and independently. The aliasing probabilities of multi-input signature registers are analyzed using the weight distributions of maximum distance separable codes. The circuit under test is a random-access memory chip. The analysis shows that aliasing probabilities of multi-input signature registers are exactly the same for both nonprimitive and primitive polynomials that define the multi-input signature registers. This implies that aliasing probabilities do not depend on the polynomials that define the multi-input signature registers. It is shown that for given test lengths n and n', where n >

Abstract: Thls Paper presents a novel slgnature analysls technlque. whlch analyzes the allaslng probabllltles of multl-Input slgnature registers (MISRS). An error model Is developed on the assumptlon that In each tlme Slot, (Y-1) error symbols occur unlformly and Independently. The allaslng probabilltles of multl-Input slgnature reglsters are analyzed using the welght dlstrlbutlons of maxlmum dlstance seperable codes. The clrcult under test Is a Random Access Memory chlp. The analysls shows that allaslng probabllltles of multl-lnpuc signature reglsters are e~actly same for both non-prlmltlve and prlmltlve ~ol~nomlals that deflne the multi-Input slgnature reglsters. Thls ImPlles that allaslng probabllltles do not depend on the pol)'nomlals that deflne the multl-Input slgnature reglsters. It Is shown that for a glVen test lengths n and n*, where n < n'. allaslng probablllty Pa:(n) Is less than allaslng probablllty Pal(n'). The aliaslng probabllltles of multlplexed multl-Input slgnature reglsterS are also analyzed uslng the maxlmum dlstance -separable ReedSolomon codes. The results shows that the allaslng probablllcles of multlplesed multl-Input slgnature reglsters do not depend on the POIYnOmlal as long as It Is prlmltlve. It Is also shown for a glven test lengths n and n', the allaslng probablllty Pal(n) Is less than the aliasIng probablllty Pal(n'). Thls slgnature analysls technlque pro] Ides more precise results In comparlslon wlth the exlstlng technlques.

Abstract: Determining the type of an object to which a pointer may point at each statement during execution is the goal of static type determination. We prove NP-hardness of type determination and aliasing for C ++ . We show the interdependence of the two problems for general-purpose pointers and present a polynomial approximation algorithm to solve the combined problem. We include empirical results to demonstrate the feasibility of our analysis.