Abstract: Alias analysis is a prerequisite for performing most of the common program analyses such as reaching-definitions analysis or live-variables analysis. Landi [1992] recently established that it is impossible to compute statically precise alias information—either may-alias or must-alias—in languages with if statements, loops, dynamic storage, and recursive data structures: more precisely, he showed that the may-alias relation is not recursive, while the must-alias relation is not even recursively enumerable. This article presents simpler proofs of the same results.

Abstract: The Solid Freeform Fabrication (SFF) process significantly reduces part specific setup manufacturing lead time. This process has been primarily used in fabricating prototypes for design visualization and verification. However, the major impact of this process on the future of manufacturing technology would be the possibility of fabricating functional parts for end use. One of the obstacles to this goal is the insufficient accuracy of the final physical part produced by the process. From the software point of view, the major sources of the inaccuracy come from the inappropriate data transfer format and the 3D aliasing' or Stair-stepping' problem. The '3D aliasing' problem can be reduced by adapting the layer thickness to the geometry of the part. In this paper, the procedure of adaptive slicing from the exact representation of the part model is described. This will improve part accuracy and minimize building time especially for the parts with highly curved surfaces. The procedures are implemented and a comparison to the conventional uniform layer thickness method will be discussed.

Abstract: A simple statistic is derived for quantifying the potential for the aliasing of tidal errors in a given linear estimate of sea surface height constructed from altimeter data. The existence of M2 tidal constituent errors in Geosat data processed in the traditional way (i.e., with orbit errors removed using least squares fits to 1 cycle per revolution sinusoids) which are of sufficient magnitude to alias into apparently westward propagating ocean features is demonstrated by artificially inducing aliasing. The aliasing statistic presented here responds clearly to the induced aliasing and to actual aliasing caused by real data dropouts in the Geosat data. The potential for aliasing M2 tidal errors is shown to vary with latitude depending on the time interval between ascending and descending ground tracks near the location of interest. The methods developed here are applied to Geosat data from the northeast Atlantic to demonstrate the presence of M2 tidal error aliasing in those data.

Abstract: The two-pass (or multipass) image geometric transformation algorithm is ideally suited to real-time, parallel implementation, but is known to introduce frequency aliasing during rotation, over and above any aliasing which may result from the usual one-pass algorithm. We develop a unified framework and theory that precisely explains this added-aliasing for many of the well-known multipass algorithms, and show that it is usually less than might be expected at first sight. In some cases, the aliasing occurs in nondestructive, and therefore, theoretically recoverable, forms. We also show that the aliasing is very easily reduced, or avoided altogether, while commenting that this problem should be considered as a special case of a general alias-avoidance strategy in geometric transformation. Finally, we include some examples of multipass image rotations which seem to confirm our predictions. >

Abstract: It is shown that a pole problem may arise from the use of a reduced Gaussian grid in the spectral transform method on the sphere. The problem is related to an asymptotic property of the associated Legendre functions and can be solved by slightly increasing the number of points close to the pole. It is also shown that the reduced grid controls aliasing arising from quadratic terms only as an asymptotic property. Nevertheless, a small increase in the number of points (everywhere) is enough to reduce the aliasing to a negligible level.

Abstract: Accurate variable sharing information is crucial both in the automatic parallelisation and in the optimisation of sequential logic programs. Analysis for possible variable sharing is thus an important topic in logic programming and many analyses have been proposed for inferring dependencies between the variables of a program, for instance, by combining domains and analyses. This paper develops the combined domain theme by explaining how term structure, and in particular linearity, can be represented in a sharing group format. This enables aliasing behaviour to be more precisely captured; groundness information to be more accurately propagated; and in addition, refines the tracking and application of linearity. In practical terms, this permits aliasing and groundness to be inferred to a higher degree of accuracy than in previous proposals and also can speed up the analysis itself. Correctness is formally proven.

Abstract: Sampling a radiographic film containing grid line patterns during digitization may produce aliasing artifacts (Moire pattern). The authors propose a mathematical model based on the laser spot size of the digitizer, the distance and the angle between the grid line and the sampling direction to predict the amplitudes and the frequencies of aliasing artifacts. The predicted results are compared to the experimental results. Effective ways of avoiding or reducing aliasing artifacts without sacrificing too much image quality are proposed. >

Abstract: An object of the present invention is to realize a compiling apparatus producing an object program which can be executed at a high speed. In a compiling apparatus according to the present invention, an aliasing address comparison instruction generating unit inserts a instruction to compare the two memory addresses of each pair of data expressions whose overlap is judged to be obscure, generates a plurality of paths defined by combinations of conditions whether or not memory addresses of data expressions of each pair overlap, and generates a instruction to branch to one of the paths according to a comparison result obtained by the instruction in an execution of a compiled program, and an optimization unit for respectively optimizing the paths. When the object program is executed, one path corresponding to a practical condition is selected from the plurality of paths, and only the selected path is executed.

Abstract: Study of the history of programming languages reveals a subtle interplay between semantics and implementation. Early languages, designed for maximum eeciency, provided simple abstractions of the underlying hardware. These languages were followed by languages that were \problem oriented" in that they attempted to hide the grosser details of the underlying hardware. Yet confusion between semantics and implementation persists, encouraged by the survival of low-level features that are deemed to be essential for eeciency. Copying, sharing, and aliasing are examples of concepts that render the task of the programmer more diicult by confusing semantics and implementation. For object oriented programs, the important distinction is not between values and references, but between mutable and immutable objects. This distinction is the basis for a model of computation that is untainted by implementation considerations and that provides the necessary foundation for object oriented modeling.

Abstract: Functions belonging to various Paley-Wiener spaces have representations in sampling series. When a function does not belong to such a space, the sampling series may converge, not to the object function but to an "alias" of it, and an aliasing error is said to occur. Aliasing error bounds are derived for one- and two-channel sampling series analogous to the Whittaker-Kotel’nikov-Shannon series, and for the multi-band sampling series, and a "derivative" extension of it, due to Dodson, Beaty, et al. The Poisson summation formula is a basic tool throughout. Aliasing in the one-channel case is shown to arise from a transformation with similarities to a projection. Where possible, the sharpness of the error bounds is discussed.

Abstract: To fully exploit the potential of large address spaces, e.g. 264-byte, the sparsity problem has to be solved in an efficient manner. Current address translation schemes either cause enormous space overhead (page table trees) or do not support address space structuring, object grouping and mixed page sizes (inverted page tables), Furthermore, an essential handicap of current virtual address spaces is their coarse granularity. It restricts the concept's relevance to low level OS technology. Without this constraint, mapping could be a vertically integrating paradigm, useful on all levels from hardware up to application programming.Guarded page tables help solving both problems. They permit significant extensions of the current programming model without performance degradation: sparse occupation and coarse-grain (4K) pages can be handled by purely conventional hardware; fine-grain (down to 16-byte) pages without fine-grain aliasing become also possible using conventional cache and TLB technology combined with stochastically colored allocation. Unrestricted aliasing and unlimited user level mapping without performance degradation may become possible by hardware innovation.

Abstract: Decoding circuitry and a method supplying an immediate field that is issued from a decoder. A macroinstruction is supplied to the decoding circuit, which generates a first micro-operation that includes a first aliasing field and a first immediate field. The first aliasing field indicates the source of the micro-operation that will eventually be issued from the decoder. If the source is the first immediate field, then the alias field is further examined to determine the interpretation to be placed upon the data. The data may be interpreted literally, or as an address into a constant ROM, thereby providing an ability to output wide, 32-bit immediate data from a narrower, 9-bit input addresses. Additional sources for immediate data include macro-alias registers, macro-branch information, and micro-branch information.

Abstract: The purpose of this paper is to evaluate several discrete Wigner distribution (DWD) formulations proposed in the literature that claim to be "alias-free" and demonstrate that most of them do indeed contain aliasing terms. Furthermore, we identify classes of signals which will always give aliasing errors for each of these DWD formulations and we state the necessary conditions for each of the "advertised" alias-free methods to produce truly alias-free time-frequency representations (TFRs). >

Abstract: Through numerical experiments we explore the incremental unknowns method; linear stationary as well as evolutionary problems are considered. For linear stationary problems, the method appears as a nearly optimal two-step preconditioning technique. At each step, we observe that the convergence behavior of the iterative methods employed is dramatically different, depending upon whether or not preconditioning is used. For linear evolutionary problems, successful and sharply accurate long-term integration is observed when the incremental unknowns (other than that of the coarsest level) are, effectively, small quantities. Otherwise, systematical aliasing arises. © 1994 John Wiley & Sons, Inc.

Abstract: In this article we propose efficient scan path and BIST schemes for RAMs. Tools for automatic generation of these schemes have been implemented. They reduce the design effort and thus allow the designer to select the more appropriate scheme with respect to various constraints.

Abstract: When test responses are compacted, even some erroneous response sequences can lead to the error-free signature This phenomenon of aliasing has been studied thoroughly using the assumption that errors in successive responses are statistically independent In this paper signature analysis and aliasing are investigated for the test responses of sequential circuits with reset where errors can be correlated both in space and time The probability of aliasing in a signature analyzer with an irreducible characteristic polynomial of degree k tends to 2/sup /spl minus/k/ as test lengths increase >

Abstract: Signature analyzers are very efficient output response compactors in BIST techniques. The only limitation of signature analysis is the fault coverage reduction (aliasing) due to the information loss inherent to any data compaction. In this paper, in order to increase the effectiveness of RAM BIST, we fake advantage from the regularity of the RAM test algorithms and we show that aliasing-free signature analysis can be achieved in RAM BIST.

Abstract: The goal of the presentation is the development of a suboptimal procedure for the solution of a high complexity problem, namely the minimal selection of the groups of weakly independent outputs for large combinational circuits. The knowledge about the groups of weakly independent outputs is usable to reduce both the necessary number of output check bits for the built-in self-test in the average more than 80% with respect to the zero aliasing and the gate area of a self-testing error detecting circuit. It is demonstrated the deductive relationship between the weak independence and the partially self-checking property of the accompanying subcircuit and the relationship between the partially selfchecking property and the groupability property. For the test of this structurally realized functional property in a circuit graph, reduction operations and distance operators for a given circuit graph were used. The results for stuck-at and stuck-open faults are discussed by means of the combinational ISCAS 85 benchmarks.

Abstract: Presents new principles for online monitoring in the context of multiprocessors (especially massively parallel processors) and then focuses on the effect of the aliasing probability on the error detection process. In the proposed test architecture, concurrent testing (or online monitoring) at the system level is accomplished by enforcing the run-time testing of the data and control dependences of the algorithm currently being executed on the parallel computer. In order to help in this process, each message contains both source and destination addresses. At each message source, the sequence of destination addresses of the outgoing messages is compressed on a block basis. At the same time, at each destination, the sequence of source addresses of all incoming messages is compressed, also on a block basis. Concurrent compression of the instructions executed by the PEs is also possible. As a result of this procedure, an image of the data dependences and of the control flow of the currently running algorithm is created. This image is compared, at the end of each computational block, with a reference image created at compilation time. The main results of this work are in proposing new principles for the online system-level testing of multiprocessor systems, based on signaturing and monitoring the data dependences together with the control dependences, and in providing an analytical model and analysis for the address compression process used for monitoring the data routing process. >

Abstract: Signature analyzers are very efficient output response compactors for BIST design The only limitation of signature analysis is the fault coverage reduction (aliasing) due to the information loss inherent to any data compaction In this article, in order to increase the effectiveness of ROM BIST, we take advantage from the simplicity of the error patterns generated by ROMs and we show that aliasing free signature analysis can be achieved in ROM BIST

Abstract: This paper deals with the design of a Built-in Self Test (BIST) environment for the Programmable Logic Arrays that minimizes the aliasing probability The signature testability condition is developed that prove criteria to compare the BIST environment aliasing An important feature of the developed approach is that the criteria proved by signature testability allows to design both pseudo-random test pattern generator (PRPG) and signature analyzer (SA)

Abstract: The aliasing probability is theoretically analyzed for a mask ROM containing a word/bit-line fault or faults within a mat. Analysis of 1000 faulty mask ROM chips revealed cell faults, word-line faults, bit-line faults, delay faults and other types. For these chips, the BIST aliasing errors were experimentally examined. Six MISRs were implemented on a custom board, and aliasing errors were actually observed. The best of the six is shown to be the 16-stage, 8-input MISR with no aliasing error. >

Abstract: In this article we address the problem of compacting test response data captured in scan paths. We consider linear compactors, e.g., multiple-input signature registers, and the effect of their characteristic polynomials on the number of aliased faults. The novelty of our analysis lies in that it is based on a realistic error model which takes into account the time correlation among the errors in the test response data fed to the compactor. Such a correlation does exist in scan-based compaction, but has not been considered previously. Based on our analysis, we derive three conditions that should be satisfied to minimize aliasing. They impose little restriction on circuit design.

Abstract: We propose a mathematical model for analyzing grid line digitization artifacts on high resolution film. In this paper, aliasing frequencies and the amplitudes of the higher frequency components of grid lines have been derived based on a theoretical model given in an earlier paper. Then the experimental results obtained from digitizing a mammography film are compared with the theoretical results. We propose a method of choosing the optimum digitization parameters in order to minimize grid line aliasing artifacts.© (1994) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

Abstract: Built-in-self-test (BIST) response data can be compacted using a linear-feedback shift register (LFSR). Prior work has indicated that the probability of aliasing tends to converge to 2-k for a polynomial of degree k and large test length, and that primitive polynomials perform better than non-primitive polynomials. Nearly all analytical models and simulations have been based on the assumption that error occurrences are statistically-independent. This paper presents the first statistical results, based on fault simulation, that show that this convergence property holds for actual digital logic circuits and randomly-generated test vector sequences. However, it is shown that the average probability of aliasing is unsuitable as a design metric, and that a 95% upper confidence limit (UCL) is more useful. This paper introduces a UCL for the loss of fault coverage due to test response compaction. The theoretical or “ideal” UCL is shown to match closely the empirically-derived UCL obtained by fault simulation. The result is that a tight lower bound on fault coverage for LFSR-based BIST configurations can be obtained easily. Fault coverage for a BIST configuration can be obtained without the LFSR, eliminating costly fault simulation of the full structure with the LFSR. These results have been incorporated in the standard procedure for fault coverage measurement.

Abstract: AdaWise, a set of tools currently under development at ORA, performs automatic checks to verify the absence of common run-time errors affecting the correctness or portability of Ada programs The tools can be applied to programs of arbitrary size, and they are conservative—that is, the absence of a warning guarantees the absence of a problem If AdaWise issues a warning, there is a potential error that should be investigated by the programmer AdaWise checks at compile-time for such potential errors as incorrect order dependence and erroneous execution due to improper aliasing These errors are not detected by typical compilers We ran two of the tools on several publicly available Ada software products to determine if the tools issue useful warnings without bombarding the user with “false positives” We found that AdaWise generated a small number of total warnings, and that false positives usually indicated areas of weakness in the products testedThis paper describes our preliminary tests using the AdaWise toolset, and analyzes the warnings that were issued

Abstract: A computer image is digital with resolution the resolution imposed by the hardware. Computer images are generated either by scanning an analog image, or by using a camera as input device, or by drawing an image to a pad, or several other means. Appropriate hardware firmware and software is available today by manufactures for converting an analog image to digital. It is well recognized that such a conversion could create aliasing, a phenomenon whereby lines have a staircase syndrome (here by lines we mean straight lines and other lines), and pixels representing small areas of the original analog picture, have undesirable discontinuities. In order for these undesirable discontinuities which are referred to as aliasing, or the phenomenon of aliasing, to be corrected special mathematical filters are applied. These filters take into consideration the fact that pixels are autocorrelated. The filters replace the intensity, or color and intensity, of the pixel with a new color and intensity. The phenomenon of aliasing is common not only when one converts images from analog to digital by inputing them in the computer by some method, but also by using mathematical methods to draw lines or surfaces in the computer, since our mathematical methods usually have as a domain and range a continuous space, but we use the computer screen, which is limited by the number of pixels available and therefore is very discrete, to represent these continuous phenomena. So aliasing is the staircase phenomenon or the undesirable discontinuities created by mapping continuous images into a discrete space. Antialiasing is a mathematical method used to correct for aliasing. Antialiasing methods usually use the values of neighboring pixels to calculate a new value for a pixel. In the space domain the process of antialiasing results in a convolution which if transformed by a Z-transform, or a Fourier transform it becomes a product. Thus it is easier from both the algebraic and computational point of view to deal with antialiasing in the frequency domain, rather than the space domain. The interesting reader could find this information in any signal processing or computer graphics book published after the mid-eighties. What we like to impress upon our readers here is that the antialiasing is a process of improving a digital image and this process has nothing to do with compression, at least as far as we are concerned and the way we use compression in our lab. We hope that our reader agrees that if we continue to use antialiasing in the already antialiased image after a few repetitions all the pixels will converge to the same value.

Abstract: This paper presents a design technique for reconfigurable linear feedback registers (RLFSR's) that are capable of operating with different compression polynomials for the purpose of output response compression into a signature and reducing aliasing over standard LFSR's. >