D. Lea
IBM
3 Papers
210 Citations
D. Lea is an academic researcher from IBM. The author has contributed to research in topics: MOSFET & Short-channel effect. The author has an hindex of 3, co-authored 3 publications.
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Papers
High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography
Shreesh Narasimha,Katsunori Onishi,Hasan M. Nayfeh,A. Waite,M. Weybright,Jeffrey B. Johnson,Carlos A. Fonseca,D. Corliss,C. Robinson,Michael Crouse,D. Yang,C-H.J. Wu,Allen H. Gabor,Thomas N. Adam,Ishtiaq Ahsan,Michael P. Belyansky,L. Black,Shahid Butt,J. Cheng,Anthony I. Chou,G. Costrini,Christos D. Dimitrakopoulos,Anthony G. Domenicucci,P. Fisher,A. Frye,S. Gates,Stephen E. Greco,Stephan Grunow,M. Hargrove,Judson R. Holt,S.-J. Jeng,M. Kelling,B. Kim,William F. Landers,G. Larosa,D. Lea,Ming-Hsiu Lee,X. Liu,Naftali E. Lustig,A. McKnight,L. Nicholson,D. Nielsen,Karen A. Nummy,Viorel Ontalus,C. Ouyang,X. Ouyang,C. Prindle,R. Pal,Werner A. Rausch,D. Restaino,Christopher D. Sheraw,J. Sim,Andrew H. Simon,Theodorus E. Standaert,Chun-Yung Sung,Keith H. Tabakman,C. Tian,R. Van Den Nieuwenhuizen,H. van Meer,A. Vayshenker,Deepal Wehella-Gamage,J. Werking,R. C. Wong,S. Wu J. Yu,R. Augur,D. Brown,X. Chen,Daniel C. Edelstein,A. Grill,Mukesh Khare,Yujun Li,S. Luning,J. Norum,Sujatha Sankaran,Dominic J. Schepis,Richard A. Wachnik,Richard Wise,C. Wann,T. Ivers,Paul D. Agnello +79 more
- 01 Dec 2006
TL;DR: In this paper, the authors present a 45-nm SOI CMOS technology that features: i) aggressive ground-rule scaling enabled by 1.2NA/193nm immersion lithography, ii) high-performance FET response enabled by the integration of multiple advanced strain and activation techniques, iii) a functional SRAM with cell size of 0.37mum2, and iv) a porous low-k (k=2.4) dielectric for minimized back-end wiring delay.
124
High speed 45nm gate length CMOSFETs integrated into a 90nm bulk technology incorporating strain engineering
Victor Chan,Rajesh Rengarajan,Nivo Rovedo,Wei Jin,Terence B. Hook,Phung T. Nguyen,Jia Chen,E.J. Nowak,X. Chen,D. Lea,Ashima B. Chakravarti,Victor Ku,See-Hun Yang,An L. Steegen,Christopher V. Baiocco,Padraic Shafer,Hung Ng,Shih-Fen Huang,C. Wann +18 more
- 08 Dec 2003
TL;DR: In this article, a leading edge 90 nm logic bulk foundry with 45 nm gate length devices, incorporating strain engineering, is described, which enable high performance devices, which are amongst the best reported to date short channel effect control down to 35 nm.
89
Chip-level power-performance optimization through thermally-driven across-chip variation (ACV) reduction
Xiaojun Yu,Oleg Gluschenkov,Noah Zamdmer,Jie Deng,B. A. Goplen,Howard S. Landis,L. R. Logan,J. A. Culp,Yue Liang,Ming Cai,Woo-Hyeong Lee,Nivo Rovedo,Frank D. Tamweber,D. Lea,Brian J. Greene,J. Sim,Dustin K. Slisher,Anthony I. Chou,Paul Chang,H. Trombley,E. J. Nowak,Sadanand V. Deshpande,William K. Henson,Anda Mocuta,K. Rim +24 more
- 01 Dec 2011
TL;DR: In this paper, a detailed study of the impact of systematic across-chip variation (ACV) on chip level power-performance is presented, where an optimized thermal anneal process was used to suppress ACV significantly, leading to a dramatic benefit in leakage power performance tradeoff.
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