M. Kelling
Advanced Micro Devices
2 Papers
144 Citations
M. Kelling is an academic researcher from Advanced Micro Devices. The author has contributed to research in topics: Copper interconnect & Back end of line. The author has an hindex of 2, co-authored 2 publications.
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Papers
High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography
Shreesh Narasimha,Katsunori Onishi,Hasan M. Nayfeh,A. Waite,M. Weybright,Jeffrey B. Johnson,Carlos A. Fonseca,D. Corliss,C. Robinson,Michael Crouse,D. Yang,C-H.J. Wu,Allen H. Gabor,Thomas N. Adam,Ishtiaq Ahsan,Michael P. Belyansky,L. Black,Shahid Butt,J. Cheng,Anthony I. Chou,G. Costrini,Christos D. Dimitrakopoulos,Anthony G. Domenicucci,P. Fisher,A. Frye,S. Gates,Stephen E. Greco,Stephan Grunow,M. Hargrove,Judson R. Holt,S.-J. Jeng,M. Kelling,B. Kim,William F. Landers,G. Larosa,D. Lea,Ming-Hsiu Lee,X. Liu,Naftali E. Lustig,A. McKnight,L. Nicholson,D. Nielsen,Karen A. Nummy,Viorel Ontalus,C. Ouyang,X. Ouyang,C. Prindle,R. Pal,Werner A. Rausch,D. Restaino,Christopher D. Sheraw,J. Sim,Andrew H. Simon,Theodorus E. Standaert,Chun-Yung Sung,Keith H. Tabakman,C. Tian,R. Van Den Nieuwenhuizen,H. van Meer,A. Vayshenker,Deepal Wehella-Gamage,J. Werking,R. C. Wong,S. Wu J. Yu,R. Augur,D. Brown,X. Chen,Daniel C. Edelstein,A. Grill,Mukesh Khare,Yujun Li,S. Luning,J. Norum,Sujatha Sankaran,Dominic J. Schepis,Richard A. Wachnik,Richard Wise,C. Wann,T. Ivers,Paul D. Agnello +79 more
- 01 Dec 2006
TL;DR: In this paper, the authors present a 45-nm SOI CMOS technology that features: i) aggressive ground-rule scaling enabled by 1.2NA/193nm immersion lithography, ii) high-performance FET response enabled by the integration of multiple advanced strain and activation techniques, iii) a functional SRAM with cell size of 0.37mum2, and iv) a porous low-k (k=2.4) dielectric for minimized back-end wiring delay.
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A 45 nm CMOS node Cu/Low-k/ Ultra Low-k PECVD SiCOH (k=2.4) BEOL Technology
Sujatha Sankaran,S. Arai,R. Augur,M. Beck,G. A. Biery,T. Bolom,Griselda Bonilla,O. Bravo,Kaushik Chanda,M. Chae,F. Chen,Larry Clevenger,Stephan A. Cohen,A. Cowley,P. Davis,James J. Demarest,J.P. Doyle,Christos D. Dimitrakopoulos,L. Economikos,Daniel C. Edelstein,Mukta G. Farooq,R. G. Filippi,John A. Fitzsimmons,Nicholas C. M. Fuller,Stephen M. Gates,Stephen E. Greco,Alfred Grill,Stephan Grunow,R. Hannon,K. Ida,D. Jung,E. Kaltalioglu,M. Kelling,T. Ko,Kaushik A. Kumar,C. Labelle,H. Landis,Michael Lane,William F. Landers,Myoung-Bum Lee,W. Li,Eric G. Liniger,X. Liu,James R. Lloyd,W. Liu,Naftali E. Lustig,K. Malone,S. Marokkey,G. Matusiewicz,Paul S. McLaughlin,P. V. McLaughlin,Sanjay Mehta,I. Melville,K. Miyata,B. Moon,Satya V. Nitta,D. Nguyen,L. Nicholson,D. Nielsen,P. Ong,Kaushal Patel,V. Patel,Wan-jae Park,John G. Pellerin,Shom Ponoth,Kevin S. Petrarca,David L. Rath,Darryl D. Restaino,S. Rhee,E.T. Ryan,H. Shoba,Andrew H. Simon,Eva E. Simonyi,Thomas M. Shaw,Terry A. Spooner,Theodorus E. Standaert,J. Sucharitaves,C. Tian,H. Wendt,J. Werking,Johnny Widodo,L. Wiggins,Robert L. Wisnieff,T. H. Ivers +83 more
- 01 Dec 2006
TL;DR: In this article, a high performance 45nm BEOL technology with proven reliability is presented, which has a hierarchical architecture with up to 10 wiring levels with 5 in PECVD SiCOH (k=3.0), and 3 in a newly developed advanced PecVD ultralow-k (ULK) porous Si-coh (k =2.4).
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