T. Ivers

IBM

2 Papers

195 Citations

T. Ivers is an academic researcher from IBM. The author has contributed to research in topics: Gate oxide & Capacitance. The author has an hindex of 2, co-authored 2 publications.

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Papers

Proceedings Article•10.1109/IEDM.2006.346879

High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography

Shreesh Narasimha, +79 more

- 01 Dec 2006

TL;DR: In this paper, the authors present a 45-nm SOI CMOS technology that features: i) aggressive ground-rule scaling enabled by 1.2NA/193nm immersion lithography, ii) high-performance FET response enabled by the integration of multiple advanced strain and activation techniques, iii) a functional SRAM with cell size of 0.37mum2, and iv) a porous low-k (k=2.4) dielectric for minimized back-end wiring delay.

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Proceedings Article•10.1109/.2005.1469238

High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell

Effendi Leobandung, +81 more

- 14 Jun 2005

TL;DR: In this article, a high performance 65 nm SOI CMOS technology is presented featuring 35 nm gate length, 1.05 nm gate oxide, performance enhancement from dual stress nitride liners (DSL), and 10 wiring levels with low-k dielectric offered in the first 8 levels.

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