Abstract: We present the design of three key building blocks for UHF-band passive RFID tag chip, i.e., voltage multiplier, ASK demodulator, and internal clock generator. An analysis on a simple equivalent circuit of RFID tag chip for long reading range is presented taking into account the finite turn-on voltage of tag chip. The Schottky diodes used in the passive RFID tag chip were fabricated using titanium (Ti/Al/Ta/Al)-silicon (n-type) junction in 0.35 mum CMOS process, and the effect of size of Schottky diode on the turn-on voltage and the input impedance of the voltage multiplier was investigated. For 300 mV RF input voltage, the fabricated voltage multiplier using Schottky diodes generated output voltages of 1.5 V and corresponding voltage conversion efficiency of 45%. In addition, we propose an example circuit for internal oscillator of tag chip with digital calibration, which can generate precise copy of RFID reader timing signals.

Abstract: A programmable system-on-a-chip integrated circuit device comprises at least one of a crystal oscillator circuit, an RC oscillator circuit, and an external oscillator input. A clock conditioning circuit is selectively coupleable to one of the programmable logic block, the crystal oscillator circuit, the RC oscillator circuit, and the external oscillator input. A real-time clock is selectively coupleable to one of the programmable logic block, the crystal oscillator circuit, the RC oscillator circuit, and the external oscillator input. A programmable logic block is coupled to the clock conditioning circuit and the real-time clock.

Abstract: This brief describes a fast-lock mixed-mode delay-locked loop (DLL) for wide-range operation and multiphase outputs. The architecture of the proposed DLL uses the mixed-mode time-to-digital-converter scheme for a frequency-range selector and a coarse tune circuit to reduce the lock time. A multi-controlled delay cell for the voltage-controlled delay line is applied to provide the wide operating frequency range and low-jitter performance. The charge pump circuit is implemented using a digital control scheme to achieve adaptive bandwidth. The chip is fabricated in a 0.25-mum standard CMOS process with a 2.5-V power-supply voltage. The measurements show that this DLL can be operated correctly when the input clock frequency is changed from 32 to 320 MHz, and can generate ten-phase clocks within a single cycle without the false locking problem associated with conventional DLLs and wide-range operation. At 200 MHz, the measured rms random jitter and peak-to-peak deterministic jitter are 4.44 and 15 ps, respectively. Moreover, the lock time is less than 22 clock cycles. This DLL occupies less area (0.07 mm2) and dissipates less power (15 mW) than other wide-range DLLs.

Abstract: •• • τ), between the first-stage multiplying DAC (MDAC) and the firststage flash ADC. The S/H, however, not only consumes a large portion of the ADC overall power consumption to drive the next MDAC with high accuracy but also adds noise and distortion to the input signal. Conventional design techniques without using the S/H have several disadvantages; a preamp in the first-stage flash ADC requires 2 capacitors to sample analog input and reference voltages, and the first-stage MDAC consumes a large amount of power to retain the same conversion speed [1]. Figure 25.3.1 shows the proposed 10b 30MS/s pipelined ADC operating from a 1.0V supply. The ADC consists of 3 MDACs, 4 flash ADCs, a digital correction logic (DCL) block, a BGR, a reference, and a clock generator. In this architecture, the elimination of the S/H scheme is employed with little modification of the conventional MDAC and preamp circuits. For further power and area reduction, the ADC adopts an opamp-sharing technique between MDAC2 and MDAC3, and a resistor-ladder sharing technique between F2 and F3 [2]. The BGR for reference and bias voltages of the ADC use a 3.3V supply. The CK signal, 2× the frequency of the ADC operation clock, is divided by 2, through a DFF, to generate non-overlap clocks Q1 and Q2. The additional clocks, QS and QL, are obtained by a combination of CK and Q2. The front-end stage of the proposed ADC, as shown in Fig. 25.3.2, is similar to that of the conventional ADC except for the S/H stage. The 3b MDAC1 uses a reversed-nested Miller compensation (RNMC) 3-stage opamp in order to obtain a high DC gain and a large output swing using a 1.0V supply [3]. The 3b flash ADC1, composed of 8 preamps using a single capacitor and latches, generates a thermometer digital code for the residue amplification of the MDAC1. The bootstrapping technique is not applied to all sampling switches to save area. Figure 25.3.3 shows the detailed timing diagrams of the front-end stage. In the conventional frontend stage with the S/H, the preamps typically sample the reference voltages first while the S/H samples the analog input signal during Q1 phase. In the hold-phase Q2 of the S/H, the preamps amplify the difference of the reference and the S/H output, and the MDAC1 samples the S/H output. The thermometer code gen

Abstract: A 37-38.5-GHz clock generator is presented in this paper. An eight-phase LC voltage-controlled oscillator (VCO) is presented to generate the multiphase outputs. The high-pass characteristic CL ladder topology sustains the high-frequency signals. The split-load divider is presented to extend the input frequency range. The proposed PD improves the static phase error and enhances the gain. To verify the function of each block and modify the operation frequency, two additional testing components-an eight-phase VCO and a split-load frequency divider-are fabricated using 0.13-mum CMOS technology. The measured quadrature-phase outputs of VCO and input sensitivity of the divider are presented. This clock generator has been fabricated with 0.13-mum CMOS technology. The measured rms clock jitter is 0.24 ps at 38 GHz while consuming 51.6 mW without buffers from a 1.2-V supply. The measured phase noise is -97.55 dBc/Hz at 1-MHz offset frequency

Abstract: An integrated receiver with multiple, independently synchronized clock signals for multiple channel transport stream decoding and delivery substantially implemented on a single CMOS integrated circuit is described. An integrated circuit that services two satellite programs must generate and distribute corresponding time domain clocks to the various components of the integrated circuit. The transport block that receives one or more satellite signals from a demodulating block will extract program clock recover values from each signal being decoded and use these values to produce an error signal or control word that serves as an input to a clock generator. Based upon this input, the clock circuit will produce a corresponding time domain clock for each channel serviced by the integrated circuit. The output of the clock circuit is distributed to the various processing blocks within the integrated circuit that operate upon channel content received and processed by the transport block.

Abstract: A circuit for driving an array of Light Emitting Diode (LED) strings at a constant current has a plurality of LEDs. A plurality of LED drivers is provided wherein a single LED driver is coupled to each of the plurality of LEDs. A voltage reference generator is used for sending a voltage reference signal to each LED driver. The voltage reference generator is external to each of the plurality of LED drivers. An input line voltage is coupled to the voltage reference generator. A clock generator is provided for sending to a clock signal to each of the plurality of LED drivers. The clock generator is external to each of the plurality of LED drivers. A low-frequency PWM dimming input signal is coupled to each of the plurality of LED drivers to allows dimming of the LEDs.

Abstract: A clock generator includes a phase-lock loop for generating an output clock signal based on a reference clock signal. The phase-lock loop includes a charge pump, a low-pass filter, and a self-bias circuit. The low-pass filter generates a bias voltage and the self-bias circuit generates a charge current based on the bias voltage. The charge pump generates an output based on the charge current to maintain a constant open-loop bandwidth of the phase-lock loop.

Abstract: The code generation apparatus includes: a clock generator which generates a clock signal of a first frequency; a timing controller which generates a timing signal of a second frequency lower than the first frequency; a code table storage in which a plurality of code sequences serving as a source for a pseudo-noise code is stored; an address controller which selects, according to the timing signal, a code sequence to be read, from among a plurality of code sequences; a partial code sequence extractor which extracts, as a partial code sequence, a code of a predetermined length, from the code sequence to be read; and a parallel-series convertor which outputs the partial code sequence one bit at a time, according to the clock signal.

Abstract: To test timing-related faults between synchronous clocks, an at-speed test clock and an automatic test pattern generation scheme are needed. However, previous work on designing on-chip at-speed test clock controllers for multi-clock has quadratic increasing area overhead along with linearly increasing clocks. This paper presents a clock-chain based test clock control scheme using an internal phase-locked-loop (PLL) as the at-speed test clock generator, which supports at-speed testing for inter-clock domain and intra-clock domain logic. Experimental results demonstrate that the proposed design has low area overhead when increasing the number of clocks.

Abstract: Exemplary embodiments of the invention provide a clock generation apparatus, system, and method, which include power management. The apparatus is couplable to second circuitry which has a clock input terminal and an inverted clock output terminal. An exemplary apparatus comprises a clock generator, a sensor, and a processor. The clock generator provides a clock signal on a first terminal which is couplable to the clock input terminal of the second circuitry. The sensor is coupled to a second terminal which is couplable to the inverted clock output terminal, and detects a power conservation mode and a power resumption mode of the second circuitry. The processor is adapted to reduce power to the clock generator and to provide a first predetermined voltage or a second predetermined voltage to the first and second terminals in response to the detection of the power conservation mode, and to increase power to the clock generator in response to the detection of the power resumption mode.

Abstract: In this paper we present the design and experimental validation of RF2, a 1 GHz, two-phase resonant-clocked FIR filter test-chip with a distributed resonant clock generator and an on-chip inductor. RF2 is fabricated in a 0.13 mum CMOS process and dissipates 124mW at resonance, with clock power accounting for only 16% of overall power. Implemented using a fully ASIC design flow, RF2 achieves 84% clock-power efficiency over CV2f, the highest for any fully-integrated resonant-clocked chip. Resonating at 1.01 GHz, RF2 reports the highest operating frequency for a resonant-clocked datapath to date.

Abstract: In this paper, an ultra-low jitter clock generator that employs a novel automatic frequency calibration (AFC) technique is presented To achieve low jitter, the clock generator uses an LC-VCO with S-bit switched tuning scheme The clock output is taken from the output of a multi-modulus divider, which increases the output frequency range with small variation in the loop bandwidth The capacitor array of the the VCO is controlled by a novel AFC technique that performs binary search for fast calibration and fine search to select an optimum tuning curve A prototype chip implemented in 013-mum CMOS process achieves 480 MHz to 1 GHz of output frequency while consuming 22 mW from a 12 V supply The measured tins jitter and calibration time of the proposed clock generator are 940 fs at 600 MM/, and 350 ns, respectively These numbers are the fastest calibration time and one of the lowest jitter that have been reported in a clock generator

Abstract: Provided is an ultra low-power wake-up receiver capable of reducing an operating time of an analog receiver by controlling operation on/off of the analog receiver according to a clock signal from a digital receiver in an amplitude-shift keying (ASK) or on-off keying (OOK) radio receiver. The ultra low-power wake-up receiver includes: a clock generator generating a clock signal having a predetermined frequency; an operation controller controlling analog operation-on for a predetermined time according to the clock signal from the clock generator; an analog receiver maintaining an operation-on state for a predetermined time according to the analog operation-on control performed by the operation controller, and being operated off after the predetermined time; and a digital receiver being operated on while the analog receiver maintains the operation-on state

Abstract: A clock generator is disclosed that includes an array of MEMS resonators and a test circuit. The test circuit is operable at start-up to operate one or more of the MEMS resonators to generate test output and analyze the test output to determine whether the operated MEMS resonators meet test criteria. A MEMS resonator is selected that meets the test criteria and its output is used to generate an output clock signal. In addition, the test circuit is operable to analyze the output of the selected MEMS resonator and select a replacement MEMS resonator when the output of the selected MEMS resonator no longer meets the test criteria. The replacement MEMS resonator is then operated and its output is coupled to the output of the clock generator. Thereby, failing and potentially failing MEMS resonators are automatically replaced during operation of the clock generator in its end-use application.

Abstract: A clock generator includes a clock circuit and a voltage-controlled oscillator in a phase-locked loop. The clock circuit monitors input clock signals and selects one of the input clock signals based on characteristics of the input clock signals. The voltage-controlled oscillator generates a reference clock signal based on the selected clock signal. The clock circuit also includes synthesizers for generating clock signals, each of which has a frequency being a non-integer multiple of a frequency of the reference clock signal. Additionally, the clock circuit individually offsets the clock signals generated by the synthesizers relative to the reference clock signal. The clock generator is capable of switching the input clock signal during operation of the clock generator while maintaining the reference clock signal. Further, the clock generator is programmable to control operation of the clock circuit.

Abstract: A 2-to-5GHz multi-phase multi-period-locked DLL is fabricated in a 90nm CMOS technology. At 5GHz, the measured rms jitter is 0.874ps and the peak-to-peak jitter is 7.56ps. The multi-phase DLL is used for a 40GHz clock generator. The core area is 0.374times0.326mm2 and the power consumption is 45mW at 1V.

Abstract: A resonant adiabatic mixed-signal VLSI array delivers 480 GMACS (109 multiply-and-accumulates per second) throughput for every mW of power, a 25-fold improvement over the energy efficiency obtained when resonant clock generator and line drivers are replaced with static CMOS drivers. Losses in resonant clock generation are minimized by activating switches between the LC tank and DC supply with a periodic pulse signal, and by minimizing the variability of the capacitive load to maintain resonance. We show that minimum energy is attained for relatively wide pulse width, and that typical load distribution in template-based charge-mode computation implies almost constant capacitive load. The resonantly driven 256 times 512 array of 3-T charge-conserving multiply-accumulate cells is embedded in a template matching processor for image classification and validated in a face detection task.

Abstract: A liquid crystal display with improved display quality and a method of driving the same include a timing controller which receives a main clock signal and outputs a first clock generation control signal and a second clock generation control signal which has a variable duty ratio, a clock generator which receives the first clock generation control signal and the second clock generation control signal and outputs a first clock signal and a second clock signal which have variable duty ratios and opposite phases, a gate driver which receives the first clock signal and the second clock signal and outputs gate signals which have variable duty ratios, and a liquid crystal panel including a plurality of pixels which are turned on according to the gate signals and display an image.

Abstract: A system, method and system are disclosed for using a variable frequency clock generator to synchronize an average data rate over intervals of time in a variable clock domain to make it equal to a fixed data rate in a fixed clock domain while reducing electromagnetic interference, among other things. In various embodiments, setting the data rates equal to each other minimizes storage used to transition data signals between clock domains. In one embodiment, a variable frequency clock generator includes a phase modulator configured to form a variable frequency clock. Also, the variable clock generator is configured to maintain an average frequency over specific periods of time for the range of discrete frequencies. The phase-offset controller sets an average clock having substantially no offset between a fixed data rate in the fixed clock domain and an average data rate in the variable clock domain.

Abstract: An ultra-low-power clock generator for passive UHF RFID tag is implemented in 0.18-mum CMOS process. By using the technique of dual-path clock generation with multiple clock rates and multiple supply voltages, clock accuracy is much improved and power consumption is reduced. Under the injection-locked condition, the measured cycle-to-cycle jitter of the clock generator is 23.7 ps and the peak-to-peak value is 164 ps with an input at 900 MHz and an output at 3.5 MHz. The overall power consumption is only 7 muW and the core chip area is 0.02 mm2.

Abstract: An integrated circuit includes a phase step generator and a clock circuit. The phase step generator generates an input clock signal based on a reference clock and the clock circuit generates an output clock signal based on the input clock signal. Additionally, the clock circuit generates a feedback clock signal based on the output clock signal and locks a phase of the feedback clock signal with a phase of the input clock signal. In response to an assertion of a trigger signal, the phase step generator extends a phase of the input clock signal by inserting a phase step into the reference clock signal. A bandwidth of the clock circuit is determined based on the output clock signal after assertion of the trigger signal.

Abstract: Embodiments of a clock generator and a clock generating method can use a delay locked loop (DLL). In one embodiment, a clock generator can include a first oscillator to generate a first clock signal having a frequency corresponding to a control signal, a delay locked loop to generate a second clock signal having a frequency higher than that of the first clock signal, a frequency divider to receive the second clock signal to generate a third clock signal having a frequency lower than that of the second clock signal, a second oscillator to generate a fourth clock signal and a phase frequency detector to generate the control signal corresponding to a phase difference and/or a frequency difference between the third clock signal and the fourth clock signal.

Abstract: A full-rate multiplexer (MUX) with a multiphase clock architecture for over 40 Gbit/s optical communication systems is presented. The 4:1 MUX is comprised of a re-timer based on a D-type flip-flop (DFF) and a clock tree system that uses EXOR-type delay buffers to match its skews well to those of the data. The supply voltage is reduced to -1.5 V by analyzing the voltage allocation. Fabricated in a 0.13-mum InP HEMT technology, a DFF test circuit achieved 75-Gbit/s operation and exhibited performance sufficient to re-time 50-Gbit/s serialized data. The 4:1 MUX measurement results demonstrate successful 50-Gbit/s operation at room temperature, and 40-Gbit/s operation, which has 10-11 error free for 231 - 1 pseudorandom bit stream (PRBS) data, up to an ambient temperature of 90 degrees or down to - 1.24 V of supply voltage. The circuit consumes 450 mW at a - 1.5-V supply and exhibits an output jitter of 283 fs rms at 50-Gbit/s operation. We also propose a multiphase clock generator for a MUX that has a serialization of more than four channels.

Abstract: An integrated circuit includes a clock generator and a synchronous clock circuit unit. The clock generator generates a first clock signal, a second clock signal, and a third clock signal, which are synchronized with one another and are provided with mutually different frequencies. The synchronous clock circuit unit includes synchronous clock circuits to which the first clock signal, the second clock signal, and the third clock signal are inputted, respectively. The synchronous clock circuits are scanned by use of the first clock signal, the second clock signal, and the third clock signal.

Abstract: An optical scanner has an oscillation-type optical scanning mechanism which includes a movable member which resonates at a predetermined resonance frequency, a drive signal generator which generates a drive signal for allowing the movable member to resonate at the resonance frequency, and an oscillation signal generator which generates an oscillation signal in response to a change of the radiation direction of the light beams. Here, the oscillation signal generator includes a dot clock generator which generates a dot clock which becomes the reference of time-series processing by setting a frequency of the oscillation signal as a reference frequency.

Abstract: A clock generator fabricated in 90nm CMOS occupies 300times128mum2 die area and dissipates 40mW at 1.2V. An interleaved clock-edge control technique extends the frequency tuning range and enables control of both rising and falling edge timing. A clock-period dithering technique enhances frequency tuning resolution. Disturbance-control functions that control jitter, duty cycle, and clock skew make timing margin testing possible

Abstract: Speed grading has becoming more and more important for nanometer technologies to support activities like process monitoring or performance diagnosis. In this work, we analyze the feasibility of providing such a capability through on-chip circuitry. This Built-in Speed Grading (BISG) methodology uses an All-Digital Phase-Locked Loop (ADPLL) as the programmable clock generator to provide various clock signals within a specific frequency range. The maximum operating speed of a circuit can thus be easily tracked down using a binary search process with multiple runs of built-in self-test. To accommodate larger process variation, we further explore a so-called binary-neighborhood-linear frequency-locking scheme for the underlying ADPLL, and thereby resulting in a higher accuracy. Experimental results show that only 2289 gates are adequate to provide this valuable infrastructure that may find numerous applications in IC testing and diagnostics.

Abstract: In some embodiments an adaptive clocking controller determines a clock spread of a system clock that would result in a lowest total interference between a channel received by a radio receiver and the system clock A clock generator modifies a spread of the system clock in response to the determined clock spread Other embodiments are described and claimed