Patent
Method of Refreshing a Memory Device, Refresh Address Generator and Memory Device
Chul-Woo Park,Joo-Sun Choi,Hongsun Hwang +2 more
- 22 Sep 2011
44
TL;DR: In this paper, a refresh address is generated with a refresh period for refreshing a memory device with refresh leveraging, where the address information is stored for only one of the first, second, and third addresses such that memory capacity may be reduced.
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Abstract: A refresh address is generated with a refresh period for refreshing a memory device with refresh leveraging. A respective refresh is performed on a weak cell having a first address when the refresh address is a second address instead of on a first strong cell having the second address. A respective refresh is performed on one of the first strong cell or a second strong cell having a third address when the refresh address is the third address. Address information is stored for only one of the first, second, and third addresses such that memory capacity may be reduced. In alternative aspects, a respective refresh is performed on one of a weak cell, a first strong cell, or a second strong cell depending on a flag when the refresh address is any of at least one predetermined address to result in refresh leveraging.
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Citations
Patent
Semiconductor memory device and method for refreshing memory cells
In Chul Jeong
- 07 Mar 2013
TL;DR: In this paper, a semiconductor memory device includes a memory block including a plurality of memory cells, a default refresh controller configured to receive a refresh command from a host, and to control the memory cells to be refreshed.
31
Patent
Semiconductor memory device that controls refresh period, memory system and operating method thereof
Jung-Sik Kim,Cheol Kim,Sang-Ho Shin +2 more
- 09 Jul 2013
TL;DR: In this paper, a refresh controller is configured to insert at least one insertion refresh address in a first refresh address sequence based on address information about the cell array to generate a second update address sequence and to apply the second refresh address to the cell arrays, such that selected cells may be refreshed more frequently without increasing an overall refresh rate.
18
Patent
Memory device and memory system performing request-based refresh, and operating method of the memory device
Hyun-Joong Kim,Ho-young Song,Hoi-Ju Chung,Ju-Yun Jung,Sanguhn Cha +4 more
- 04 Nov 2016
TL;DR: In this paper, a memory device and a memory system performing request-based refresh, and an operating method of the memory device, are provided, where the operating method includes: determining a weak row by counting an activated number of at least one row; requesting for refresh on the weak row based on a result of the determining; and performing target refresh upon receiving a refresh command according to the requesting.
14
Patent
Semiconductor memory device and refresh control method thereof
Sung-Yub Lee,Sung-Soo Chi +1 more
- 16 Apr 2015
TL;DR: In this paper, a refresh operation for a first adjacent word line group of a target word line of the plurality of word lines is performed after the first refresh operation, in response to a smart refresh command.
13
Patent
Method of refreshing volatile memory device
Dae-Jeong Kim,Heon Kyu Lee,Hoon-Chang Yang,Kwang-Woo Lee +3 more
- 21 Jul 2014
TL;DR: In this paper, a method for refreshing a volatile memory is described, which includes storing address information about a weak cell row address that is to be refreshed according to a weak-cell refresh period that is shorter than a refresh period.
13
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Patent
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Patent
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Jong-Hoon Oh
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TL;DR: In this article, a method and circuit configurations for utilizing memory cells having weak retention times are provided, where rows identified as having weak memory cells may be refreshed more often than normal retention cells.
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Patent
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Scott C. Best,Ely K. Tsern +1 more
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TL;DR: In a dynamic random access memory (DRAM) as discussed by the authors, each row of storage cells is refreshed once per refresh interval, and each row is associated with a low-retention row.
49
Patent
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Ely K. Tsern
- 04 Aug 2005
TL;DR: In this article, a dynamic random access memory (DRAM) device receives refresh commands via a signaling interface and, in response to the refresh commands, refreshing a first row of storage cells at a first refresh rate and refreshing a second row at a second, faster refresh rate.
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Patent
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24
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