Patent
Semiconductor memory device and refresh control method thereof
Sung-Yub Lee,Sung-Soo Chi +1 more
- 16 Apr 2015
13
TL;DR: In this paper, a refresh operation for a first adjacent word line group of a target word line of the plurality of word lines is performed after the first refresh operation, in response to a smart refresh command.
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Abstract: A semiconductor memory device includes a memory bank including a plurality of word lines, and a refresh operation control unit suitable for performing a first refresh operation for a first adjacent word line group of a target word line of the plurality of word lines, and performing a second refresh operation for a second adjacent word line group of the target word line after the first refresh operation, in response to a smart refresh command.
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Citations
Patent
Apparatuses and methods for targeted refreshing of memory
William F. Jones,Jeffrey P. Wright +1 more
- 17 Jan 2014
TL;DR: In this article, a row refresh mechanism is proposed to determine whether a target row of memory associated with the target row address is a primary or a redundant row of RAM. But the method is not described in detail.
20
Patent
Apparatuses and methods for controlling refresh operations
Hiroshi Akamatsu
- 15 May 2015
TL;DR: In this article, the authors describe an apparatus consisting of a first word line, a second word line and a control, and the control circuit includes a first defective address storing circuit and a first detection circuit.
12
Patent
Apparatuses and methods for calculating row hammer refresh addresses in a semiconductor device
Masaru Morohashi,Hidekazu Noguchi +1 more
- 22 Jan 2018
TL;DR: In this paper, a sub-word-line address scrambler circuit including a subwordline scrambler is presented, which is configured to receive a first subset of bits of a row hammer hit address.
8
Patent
Semiconductor memory device for performing refresh operation and operating method therof
Lee Sung-Yub,Lee Geun-Il,Cha Jae-Hoon +2 more
- 29 Jun 2017
TL;DR: In this paper, a memory bank comprising a plurality of word lines, a smart command generation unit suitable for generating a smart refresh command, which is enabled at a random cycle, in response to an active command, is described.
4
Patent
Apparatuses and methods for managing row access counts
Michael A. Shore,Li Jiyun +1 more
- 06 Feb 2019
TL;DR: In this article, the authors present a method for managing access counts of wordlines of a memory, where the access count of a given wordline may be stored in counter memory cells positioned along that wordline.
4
References
Patent
Method of Refreshing a Memory Device, Refresh Address Generator and Memory Device
Chul-Woo Park,Joo-Sun Choi,Hongsun Hwang +2 more
- 22 Sep 2011
TL;DR: In this paper, a refresh address is generated with a refresh period for refreshing a memory device with refresh leveraging, where the address information is stored for only one of the first, second, and third addresses such that memory capacity may be reduced.
44
Patent
Memory and memory system including the same
Doo-Chan Lee,Choung-Ki Song +1 more
- 17 Dec 2013
TL;DR: In this article, a memory consisting of a first cell block comprising a plurality of first word line groups, and one or more first redundancy word line group each corresponding to one hit signal of a majority of hit signals, is used to select a cell block and a word line in response to a first input address and refreshing a selected word line based on an input address inputted after the first address.
37
Patent
Memory and memory system including the same
Seok-Cheol Yoon,Bo-Yeun Kim,Jae-Boum Park +2 more
- 03 Oct 2014
TL;DR: In this article, the first time point is included in time section other than a refresh section in which the control unit refreshes one or more word lines in response to application of the refresh command.
32
Patent
Memory and memory system including the same
Yu-Ri Lim,Jin-Hee Cho,Jung-Hoon Park +2 more
- 16 Jul 2014
TL;DR: A memory includes a plurality of word lines, a measurement block suitable for measuring an active duration of an activated word line among the multiple word lines and a refresh circuit suitable for controlling a refresh operation to refresh one or more of the adjacent word lines when the active duration exceeds a predetermined threshold as mentioned in this paper.
31
Patent
Semiconductor memory device
Lee Yeonghun
- 29 Sep 2016
TL;DR: A semiconductor memory device includes a plurality of memory cells and an X-decoder as discussed by the authors, which applies an operating voltage to the word line, while the memory cells are connected to a word line.
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