Interrupt priority level

Abstract: Interrupt control apparatus in a data processing system for acknowledging on a priority basis one among several possible asynchronous interruptions (INT1, INTN), such apparatus comprising a priority network (5), a latching (7) and a validation circuit (11,12). The priority network directly receives on its input terminals the asynchronous interrupt signals and provides on its output terminals a binary code corresponding to the highest priority interrupt present on its input terminals. The interrupt code is latched in the register and is present on its output terminals. The code latched in the register is used by a validation circuit as a selection code of the related input interrupt signal. If such a signal is present, the code is validated, i.e., it is transferred to the central unit of the system. If the selected interrupt signal is not present, the code is not validated.

Abstract: Interrupts generated within a data processor (internal interrupts) and an interrupt received from a peripheral device (external interrupts) coupled with the processor are prioritized and, unless suppressed, are coupled to generate an interrupt signal for use in addressing a routine for servicing the particular highest priority requesting internal or external interrupt. All further interrupts are suppressed during the time required to service the interrupt and, depending upon the type of interrupt, either the internal or external interrupt may be suppressed for one or two instruction times for debug purposes or under computer program control as required for a particular operation.

Abstract: A method, system and computer program product for processing interrupts in a multi-processor system is provided. The method, system and computer program product process interrupts utilizing an unequal scheduling policy in order to achieve SLA target goals for interrupt processing. In a method of the present invention an interrupt is received. A determination is made as to whether the interrupt is assigned to a specific processor. If the interrupt is not assigned to a specific processor then a processor is selected from the group of processors based on their respective interrupt priority levels. Specifically, one processor is selected from all the processors that have the highest interrupt priority level. After the interrupt has been processed by the selected processor, a determination is made as to whether the selected processor has exceeded its threshold processing level. If threshold processing level has been exceeded, the selected processor's interrupt priority level is lowered.