Topic
Interposer
About: Interposer is a research topic. Over the lifetime, 5093 publications have been published within this topic receiving 66248 citations.
Papers published on a yearly basis
1 / 2
Papers
Patent•
13 Jul 2011TL;DR: In this article, the interposer plate at approximately a right angle to the plank stack is electrically coupled to the semiconductor dies along an edge of a plank stack, and electrical pads proximate to a surface of the interPOSer plate (which are along a stacking direction of the plank stacks) are electrically coupling to pads that are proximate by edges of the semiconductors by an intervening conductive material, such as solder balls or spring connectors.
Abstract: In a chip package, semiconductor dies in a vertical stack of semiconductor dies or chips (which is referred to as a ‘plank stack’) are aligned by positive features that are mechanically coupled to negative features recessed below the surfaces of adjacent semiconductor dies. Moreover, the chip package includes an interposer plate at approximately a right angle to the plank stack, which is electrically coupled to the semiconductor dies along an edge of the plank stack. In particular, electrical pads proximate to a surface of the interposer plate (which are along a stacking direction of the plank stack) are electrically coupled to pads that are proximate to edges of the semiconductor dies by an intervening conductive material, such as solder balls or spring connectors. Note that the chip package may facilitate high-bandwidth communication of signals between the semiconductor dies and the interposer plate.
19 citations
Patent•
15 Aug 2007
TL;DR: In this paper, the interposer is placed through a window in the release liner of an RFID label and the antenna is placed in contact with the end portions of the antenna.
Abstract: An RFID label includes a release liner having an opening or window, to allow placement of an interposer through the window, and in contact with end portions of an antenna. By coupling the interposer to the antenna through the window in the release liner, the coupling may be performed at a later point than usual in the fabrication of the label. This allows the label to be fabricated with less wear and tear on the interposer, which is a relatively expensive and fragile part of the antenna. In addition, testing of the interposers before applying them to a web of labels may save costs by eliminating waste of material. Testing of the straps alone can allow prediction of performance of the finished label.
19 citations
Patent•
2 Oct 2000TL;DR: In this article, a matched set of integrated circuit chips (24) and a method for assembling them into matched set are disclosed. But their method is limited to the case where the chip assemblies are sorted and at least two of them are selected for inclusion in the matched set.
Abstract: A matched set of integrated circuit chips ( 24 ) and a method for assembling such integrated circuit chips ( 24 ) into a matched set are disclosed. A semiconductor wafer ( 18 ) having a plurality of integrated circuit chips ( 24 ) is electrically and mechanically coupled to a wafer interposer ( 12 ) to form a wafer-interposer assembly ( 10 ). The integrated circuit chips ( 24 ) of the wafer ( 18 ) are then tested together by attaching the wafer-interposer assembly ( 10 ) to a testing apparatus and running the integrated circuit chips ( 24 ) through various testing sequences. The wafer-interposer assembly ( 10 ) is then diced into a plurality of chip assemblies each having a chip ( 24 ) and a section of the wafer interposer ( 12 ). Based upon the testing, the chip assemblies are sorted and at least two of the chip assemblies are selected for inclusion in the matched set.
19 citations
Patent•
19 Sep 2011TL;DR: A method for fabricating an encapsulant cavity integrated circuit package system includes: providing an interposer, forming a first integrated circuit (IC) package with an inverted bottom terminal having an encapsULant cavity and the interposers, and attaching a component on the interPOSer in the encapsulated cavity as discussed by the authors.
Abstract: A method for fabricating an encapsulant cavity integrated circuit package system includes: providing an interposer; forming a first integrated circuit package with an inverted bottom terminal having an encapsulant cavity and the interposer; and attaching a component on the interposer in the encapsulant cavity.
19 citations
Patent•
17 Aug 2012TL;DR: In this paper, a multi-chip module is presented that comprises a package substrate, at least two integrated circuit devices, each of which is electrically coupled to the package substrate and an interposer.
Abstract: A Multi-Chip Module is presented herein that comprises a package substrate, at least two integrated circuit devices, each of which is electrically coupled to the package substrate, and an interposer. Formed in the interposer are electrical connections which are predominantly horizontal interconnects. The first interposer is arranged to electrically couple the two integrated circuit devices to each other. Methods for manufacturing a Multi-Chip Module are also presented herein.
19 citations
Related Topics (5)
Performance Metrics
| Year | Papers |
|---|---|
| 2025 | 37 |
| 2024 | 75 |
| 2023 | 83 |
| 2022 | 156 |
| 2021 | 128 |
| 2020 | 239 |