Topic
Interposer
About: Interposer is a research topic. Over the lifetime, 5093 publications have been published within this topic receiving 66248 citations.
Papers published on a yearly basis
1 / 2
Papers
Patent•
21 Mar 1991
TL;DR: In this article, a semiconductor chip having contacts on the periphery of its top surface is provided with an interposer overlying the central portion of the top surface, where peripheral contact leads extend inwardly from the peripheral contacts to central terminals on the interposers.
Abstract: A semiconductor chip having contacts on the periphery of its top surface is provided with an interposer overlying the central portion of the top surface. Peripheral contact leads extend inwardly from the peripheral contacts to central terminals on the interposer. The terminals on the interposer may be connected to a substrate using techniques commonly employed in surface mounting of electrical devices, such as solder bonding. The leads, and preferably the interposer, are flexible so that the terminals are movable with respect to the contacts on the chip, to compensate for differential thermal expansion of the chip and substrate. The terminals on the interposer may be disposed in an area array having terminals disposed at substantially equal spacings throughout the area of the interposer, thus providing substantial distances between the terminals while accommodating all of the terminals in an area approximately the same size as the area of the chip itself. The interposer may be provided with a compliant layer disposed between the terminals and the chip to permit slight vertical movement of the terminals towards the chip during testing operations. The chip and interposer assembly may be electrically tested prior to assembly to the substrate. A compliant layer disposed between the terminals and the chip permits slight vertical movement of the terminals towards the chip during testing operations, in which the terminals on the interposer are engaged with an assembly of test probes. The entire assembly is compact.
565 citations
Patent•
24 Sep 1990
TL;DR: In this article, a semiconductor chip assembly is mounted to contact pads in a compact area array, and an interposer is disposed between the chip and the substrate, where contacts on the chip are connected to terminals on the interposers by flexible leads extending through apertures in the interPOSer.
Abstract: A semiconductor chip assembly is mounted to contact pads in a compact area array. An interposer is disposed between the chip and the substrate. The contacts on the chip are connected to terminals on the interposer by flexible leads extending through apertures in the interposer. The terminals on the interposer in turn are bonded to the contact pads on the substrate. Flexibility of the leads permits relative movement of the contacts on the chip relative to the terminals and the contact pads of the substrate and hence relieves the stresses caused by differential thermal expansion. The arrangement provides a compact structure similar to that achieved through flip-chip bonding, but with markedly increased resistance to thermal cycling damage.
454 citations
Patent•
TSMC1
TL;DR: In this paper, a package system includes a first integrated circuit disposed over an interposer and a first interconnect structure is disposed over a first surface of the at least one molding compound layer and electrically coupled with the plurality of electrical connection structures.
Abstract: A package system includes a first integrated circuit disposed over an interposer. The interposer includes at least one molding compound layer including a plurality of electrical connection structures through the at least one molding compound layer. A first interconnect structure is disposed over a first surface of the at least one molding compound layer and electrically coupled with the plurality of electrical connection structures. The first integrated circuit is electrically coupled with the first interconnect structure.
420 citations
Patent•
IBM1
TL;DR: In this paper, a high speed, high performance integrated circuit packaging structure that may be used for emulating wafer scale integration structures is presented, which allows a plurality of discrete semiconductor segments to be mounted on and interconnected by the integrated circuit package with a significantly reduced number of drivers and receivers than required by Rent's Rule.
Abstract: A high speed, high performance integrated circuit packaging structure that may be used for emulating wafer scale integration structures. The preferred embodiment comprises an interposer having a base substrate having alternating insulation and conductive layers thereon, wherein a plurality of the conductive layers are wiring means which are adapted for maintaining an extremely low noise level in the package. The low noise level and low resistance and capacitance of the wiring means allows a plurality of discrete semiconductor segments to be mounted on and interconnected by the integrated circuit package with a significantly reduced number of drivers and receivers than required by Rent's Rule. Each integrated circuit structure of the present invention emulates a large chip or wafer scale integration structure in performance without having to yield the large chip or wafer, and without redundancy schemes. A plurality of these integrated circuit packaging structures are combined by decals to form a central processing unit of a computer or a portion thereof. In an alternate preferred embodiment, the base substrate of the interposer is made of silicon and any required drivers are formed therein, thus substantially eliminating the need for any drivers on each of the discrete semiconductor segments.
385 citations
Patent•
3 Sep 1999TL;DR: In this article, an interposer is used to attach an integrated circuit (116) to the antenna elements (112, 114), which reduces the precision required to successfully couple the integrated circuit to the antennas elements.
Abstract: A radio frequency identification tag (100) includes a substrate member (110) having an inner surface and an outer surface. Disposed on the inner surface are first (112) and second (114) antenna elements. The antenna elements are electrically isolated from each other and coupled to two separate pads on an integrated circuit (116). Adhesive (118) is applied on the inner surface of the substrate, the antenna elements and the integrated circuit for securing the tag. The tag may employ an interposer (600) to attach integrated circuit (116) to the antenna elements (112, 114). The interposer (600) has a substrate (602) and first and second connecting pads (602, 604) electrically isolated from each other and electrically connected to the connecting pads on the integrated circuit (116). Interposer (600) reduces the amount of the precision required to successfully couple integrated circuit (116) to the antenna elements (112, 114).
376 citations
Related Topics (5)
Performance Metrics
| Year | Papers |
|---|---|
| 2025 | 37 |
| 2024 | 75 |
| 2023 | 83 |
| 2022 | 156 |
| 2021 | 128 |
| 2020 | 239 |