Spintronic Threshold Logic Array (STLA) - A compact, low leakage, non-volatile gate array architecture

TL;DR: In this paper, the authors introduce a physical implementation of a memristor-based current-mode threshold logic gates (MCMTLG) circuit and validate its design and operation through multiple experimental setups.

TL;DR: Evaluations with a recent neuromorphic hardware architecture show that the proposed design-technology co-optimization approach improves both performance and energy efficiency of machine-learning inference tasks without incurring high cost-per-bit.

TL;DR: This paper formulate the fundamental operation of collapsing threshold logic gates, not addressed by prior efforts, and proposes a linear time translation from threshold logic circuits to pseudo-Boolean constraints, in contrast to prior exponential translation costs.

TL;DR: A procedure to canonicalize a threshold logic function such that two threshold logic functions are equivalent if and only if their canonicalized linear inequalities are the same, which allows direct application to the classification of NP and NPN equivalence of threshold Logic functions.

TL;DR: Comparisons among the various RTD physical models and major features of RTD's, resonant interband tunneling diodes, and Esaki tunnel diods are presented and the device operational principles, various modeling approaches, and major device properties are reviewed.

TL;DR: In this paper, the authors present the first non-volatile Flip-Flop based on spin-transfer torque (STT) for Field Programmable Gate Array (FPGA) and System On Chip (SOC) circuits.

TL;DR: In this paper, a thermally assisted switching (TAS) MTJ cell and a pre-charge sensing amplifier (PCSA) circuit are used to overcome the low reliability in memory cell and sensing amplifier circuits, which greatly limits its practical applications for logic computation.

TL;DR: In this paper, the authors discuss the clocking of six-dot quantum automata (QCA) devices and connect layout to architecture, and discuss how to control the timing and direction of data flow in QCA circuits.