Sarma Vrudhula
Arizona State University
224 Papers
2K Citations
Sarma Vrudhula is an academic researcher from Arizona State University. The author has contributed to research in topics: Logic gate & Computer science. The author has an hindex of 48, co-authored 208 publications. Previous affiliations of Sarma Vrudhula include Texas A&M University & University of Arizona.
Chat about Author
Papers
Throughput-Optimized OpenCL-based FPGA Accelerator for Large-Scale Convolutional Neural Networks
Naveen Suda,Vikas Chandra,Ganesh Dasika,Abinash Mohanty,Yufei Ma,Sarma Vrudhula,Jae-sun Seo,Yu Cao +7 more
- 21 Feb 2016
TL;DR: This work presents a systematic design space exploration methodology to maximize the throughput of an OpenCL-based FPGA accelerator for a given CNN model, considering the FPGAs resource constraints such as on-chip memory, registers, computational resources and external memory bandwidth.
660
Predictive Modeling of the NBTI Effect for Reliable Design
Sarvesh Bhardwaj,Wenping Wang,Rakesh Vattikonda,Yu Cao,Sarma Vrudhula +4 more
- 01 Sep 2006
TL;DR: This paper presents a predictive model for the negative bias temperature instability (NBTI) of PMOS under both short term and long term operation based on the reaction-diffusion (R-D) mechanism, which accurately captures the dependence of NBTI on the oxide thickness, the diffusing species and other key transistor and design parameters.
489
Optimizing Loop Operation and Dataflow in FPGA Acceleration of Deep Convolutional Neural Networks
Yufei Ma,Yu Cao,Sarma Vrudhula,Jae-sun Seo +3 more
- 22 Feb 2017
TL;DR: This work systematically explore the trade-offs of hardware cost by searching the design variable configurations, and proposes a specific dataflow of hardware CNN acceleration to minimize the memory access and data movement while maximizing the resource utilization to achieve high performance.
427
Optimizing the Convolution Operation to Accelerate Deep Neural Networks on FPGA
TL;DR: This paper quantitatively analyzing and optimizing the design objectives of the CNN accelerator based on multiple design variables and proposes a specific dataflow of hardware CNN acceleration to minimize the data communication while maximizing the resource utilization to achieve high performance.
340
The Impact of NBTI Effect on Combinational Circuit: Modeling, Simulation, and Analysis
TL;DR: This paper develops a hierarchical framework for analyzing the impact of NBTI on the performance of logic circuits under various operation conditions, such as the supply voltage, temperature, and node switching activity, and proposes an efficient method to predict the degradation of circuit speed over a long period of time.
324