Method for debugging reconfigurable architectures

TL;DR: In this paper, a data processing device comprising a multidimensional array of coarse grained logic elements processing data and operating at a first clock rate and communicating with one another and/or other elements via busses or communication lines operated at a second clock rate is described.

TL;DR: An internal bus system for DFPs and units with two- or multi-dimensional programmable cell architectures, for managing large volumes of data with a high interconnection complexity, is presented in this article.

TL;DR: In this article, the first result data may be obtained using a plurality of configurable coarse-granular elements, and the first results may be subsequently processed using the plurality of configured granular elements.

TL;DR: In this paper, a clock preselecting means is designed in such a way that, depending on the state, a first clock is preselected at least at a first cell (PAE) and an additional clock is precomputed at least in an additional cell.

TL;DR: In this paper, a method and apparatus for decoding a sequence of digitally encoded data is presented, where the digital data has a value indicative of a plurality of predetermined values, and a unique decoded value is selected from the plurality of pre-decoded values.

TL;DR: Simulation and measurement data confirmed that both power consumption and memory area can be substantially reduced, making FeRAM the most promising new technology for implementing high-performance, low-power reconfigurable hardware.

TL;DR: In this article, a torsional actuator is employed to apply input energy to the vehicle in a manner that mimics the energy generated by the axle during the operation of the vehicle so that both the driving load and the vibration induced by gearset motion variation are simulated.

TL;DR: In this article, the authors propose to use bit-by-bit comparison circuitry to validate the half-byte results received from both BPUs in the case of single-precision operations and, for both cache units, the result parity bits.