Method for debugging reconfigurable architectures

TL;DR: In this paper, a data processing device comprising a multidimensional array of coarse grained logic elements processing data and operating at a first clock rate and communicating with one another and/or other elements via busses or communication lines operated at a second clock rate is described.

TL;DR: An internal bus system for DFPs and units with two- or multi-dimensional programmable cell architectures, for managing large volumes of data with a high interconnection complexity, is presented in this article.

TL;DR: In this article, the first result data may be obtained using a plurality of configurable coarse-granular elements, and the first results may be subsequently processed using the plurality of configured granular elements.

TL;DR: In this paper, a clock preselecting means is designed in such a way that, depending on the state, a first clock is preselected at least at a first cell (PAE) and an additional clock is precomputed at least in an additional cell.

TL;DR: An intermediate program representation, called the program dependence graph (PDG), that makes explicit both the data and control dependences for each operation in a program, allowing transformations to be triggered by one another and applied only to affected dependences.

TL;DR: Advanced Compiler Design and Implementation by Steven Muchnick Preface to Advanced Topics

TL;DR: The hardware aspects of reconfigurable computing machines, from single chip architectures to multi-chip systems, including internal structures and external coupling are explored, and the software that targets these machines is focused on.

TL;DR: The authors have divided the use of computers into the following four levels of sophistication: data processing, information processing, knowledge processing, and intelligence processing.