Patent
Image correlation system
Michael F. Deering
- 17 Dec 1987
51
TL;DR: In this paper, a method and apparatus for controlling a parallel combination of correlation circuits which compare image pixels is presented, with each memory being assigned a different block (region) of the image.
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Abstract: A method and apparatus for controlling a parallel combination of correlation circuits which compare image pixels. A number of correlation circuits are provided, each having its own memory. The memories are loaded with image data with each memory being assigned a different block (region) of the image. Each memory is also loaded with an overlapping portion of an adjacent block so that a pattern can be stepped across the entire block, including a match of the first column of the pattern with the last column of the block. The loading is done by generating addresses corresponding to addresses for the source image with one or more of the most significant bits modified so that the address sequence received by the second and subsequent memories are identical to the address sequence received by the first memory. This allows the various blocks of the image in the different memories to be later simulataneously accessed in parallel using a single address sequence.
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Citations
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References
Patent
Pattern recognition system operating by the multiple similarity method
Asakawa Teruyoshi
- 06 Mar 1981
TL;DR: In this article, a plurality of pattern similarity computation circuits (24, to 24n) are provided, and different sample pattern data and a reference pattern data are coupled to the individual computation circuits, whereby the calculation of the similarity degree of the reference pattern with respect to individual sample patterns is simultaneously made in the respective computation circuits.
19
Patent
High speed correlation circuit and method
Cooper J Carl
- 25 Jan 1982
TL;DR: In this article, high speed serial data bits of a data stream are received, stored, shifted and compared in parallel to bit contents of a known correlation word, for each bit match a known signal change is provided on a common terminal.
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