Patent
Microcode patch device and method for patching microcode using match registers and patch routines
Kevin J. McGrath,James K. Pickett +1 more
- 27 Oct 1999
161
TL;DR: In this article, a random access memory (RAM) is provided in a processor for implementing microcode patches, which is part of the normal microcode contained in a microcode read only memory (ROM) unit of the processor.
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Abstract: Random access memory (RAM) may be provided in a processor for implementing microcode patches. The patch RAM may loaded by a microcode routine that is part of the normal microcode contained in a microcode read only memory (ROM) unit of the processor. When the processor powers-up, it uses its internal ROM microcode only if no patches are installed. If patches are installed and a microcode line is accessed for which a patch is enabled, the patch is executed instead of the microcode line. A patch may be enabled by setting a match register with the address of the microcode instruction line in the microcode ROM that is to be patched. Whenever the microcode ROM address matches the contents of a match register, control is transferred to the patch RAM. The patch RAM may have a plurality of fixed entry points each corresponding to a different match register.
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Citations
Patent
Automated analysis of kernel and user core files including searching, ranking, and recommending patch files
George W. Hines
- 12 Feb 2001
TL;DR: In this paper, a computerized method for automatically analyzing a core file created by a computer system after an unexpected interrupt is presented, where packages installed on the computer system are determined and patch files of descriptive data for previously identified patches are accessed to create a patch search set including patches configured for use with the installed packages.
88
Patent
Techniques for reducing color artifacts in digital images
Shang-Hung Lin,Ignatius B. Tjandrasuwita +1 more
- 23 Jul 2007
TL;DR: In this paper, a technique for reducing artifacts in a digital image, in accordance with one embodiment, includes receiving a stream of raw filter pixel data representing the image, interpolating to produce red, green-on-red row, greenon-blue row and blue pixel data for each pixel.
73
Patent
Latency tolerant system for executing video processing operations
Ashish Karandikar,Shirish Gadre,Stephen D. Lew +2 more
- 04 Nov 2005
TL;DR: In this article, a latency tolerant system for executing video processing operations is presented, which includes a host interface for implementing communication between the video processor and a host CPU, a scalar execution unit coupled to the host interface and configured to execute scalar video processing operation, and a vector execution unit, coupled with the host interfaces, configured to operate on a demand-driven basis.
71
Shielding against design flaws with field repairable control logic
Ilya Wagner,Valeria Bertacco,Todd Austin +2 more
- 24 Jul 2006
TL;DR: This paper proposes a novel hardware patching mechanism that can detect design errors which escaped the verification process, and can correct them directly in the field, through a simple field-programmable state matcher.
Patent
Dynamically changing the semantic of an instruction
Chauvel Gerard,Lasserre Serge,Dominique D'Inverno,Kuusela Maija,Cabillic Gilbert,Jean-Philippe Lesot,Banatre Michel,Jean-Paul Routeau,Majoul Salam,Frederic Parain +9 more
- 22 Apr 2004
TL;DR: In this paper, a technique comprises receiving an instruction and dynamically changing the instruction's semantic based on programmable information that is separate from the instruction, which may include the inclusion of monitoring code that determines a performance characteristic associated with the instruction or a change in the instruction operation.
48
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TL;DR: In this paper, a reprogrammable subscriber terminal of a subscription television service can have the control program code of its control processor modified by downloading new program code from the head-end.
310
Patent
Pipelined data processor capable of decoding and executing plural instructions in parallel
Kazunori Kuriyama,Y. Shintani,Akira Yamaoka,Tohru Shonai,Eiki Kamada,Kiyoshi Inoue +5 more
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TL;DR: A pipelined data processor comprises a circuit for extracting two instructions into a pair of instruction registers (l, 2), a circuit (6) for detecting whether those instructions are a combination of an instruction requesting a use of an operation unit and a instruction requesting the use of other resource as discussed by the authors.
289
Patent
Method and apparatus for store-into-instruction-stream detection and maintaining branch prediction cache consistency
John G. Favor,Korbin S. Van Dyke,David R. Stiles +2 more
- 06 Feb 1991
TL;DR: The branch prediction cache (BPC) as mentioned in this paper provides a tag identifying the address of instructions causing a branch, a record of the target address which was branched to on the last occurrence of each branch instruction, and a copy of the first several instructions beginning at this target address.
279
Patent
Processor having plurality of functional units for orderly retiring outstanding operations based upon its associated tags
Harold L. McFarland,David R. Stiles,Korbin S. Van Dyke,Shrenik Mehta,John G. Favor,Dale R. Greenley,Robert A. Cargnoni +6 more
- 21 Feb 1990
TL;DR: In this paper, a pipeline control system is distributed over the functional units (15, 17, 20, 25) in a processor (10). Decoder logic (12) issues operations, each with an associated tag, to functional units, with up to n operations allowed to be outstanding.
268
Patent
Instruction issuing mechanism for processors with multiple functional units
Hwa C. Torng
- 14 Oct 1987
TL;DR: In this article, an instruction issuing mechanism for boosting throughput of processors with multiple functional units is proposed. But, it does not support non-sequential instruction issuing and instructions do not have to be issued according to their order in the instruction stream.
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