Patent
Field effect transistor pull-up/load element
King Tsu-Jae
- 18 Nov 2002
4
TL;DR: In this paper, an improved MISFET is proposed which is particularly suited as a replacement for conventional pull-up and load elements such as NDR diodes, passive resistors, and conventional FETs.
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Abstract: An improved MISFET is disclosed which is particularly suited as a replacement for conventional pull-up and load elements such as NDR diodes, passive resistors, and conventional FETs. The MISFET includes a charge trapping layer formed at or extremely near to an interface between a substrate (which can be silicon or SOI) and a gate insulation layer. In this fashion, charge traps can be optimized for extremely rapid trapping and de-trapping of charge because they are extremely close to a channel of hot carriers. The MISFET channel can be shut off during static operations to further reduce power dissipation, and can also be adapted to operate with negative differential resistance.
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Citations
Patent
Improved cmos diodes with dual gate conductors, and methods for forming the same
David M. Onsongo,Werner A. Rausch,Haining S. Yang +2 more
- 25 Apr 2007
TL;DR: In this article, the authors proposed an improved CMOS diode structure with dual gate conductors, where the second gate is spaced apart and isolated from the first gate by a dielectric isolation structure, and a third region of either n-type or p-type conductivity is located between the first and second regions.
15
Patent
Silicon-based tunneling field effect transistors and transistor circuitry employing same
Paul R. Berger
- 13 Sep 2010
TL;DR: In this paper, a p-channel TFET is selected from a group consisting of (i) a multi-layer structure of group IV layers and (ii) a multilayer structure of groups III-V layers.
13
Patent
Tunneling field effect transistors and transistor circuitry employing same
Paul R. Berger
- 20 Nov 2015
TL;DR: In this article, a p-channel TFET is selected from a group consisting of (i) a multi-layer structure of group IV layers and (ii) a multilayer structure of groups III-V layers.
3
Patent
Cmos diodes with dual gate conductors, and methods for forming the same
David M. Onsongo,Werner A. Rausch,Haining S. Yang +2 more
- 14 Jun 2010
TL;DR: In this article, the authors proposed an improved CMOS diode structure with dual gate conductors, where the second gate is spaced apart and isolated from the first gate by a dielectric isolation structure, and a third region of either n-type or p-type conductivity is located between the first and second regions.
1
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Patent
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Leonard Forbes,Joseph E. Geusic +1 more
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