Spintronic devices exploit the spin, as well as the charge, of electrons and could bring new capabilities to the microelectronics industry However, in order for spintronic devices to meet the ever-increasing demands of the industry, innovation in terms of materials, processes and circuits are required Here, we review recent developments in spintronics that could soon have an impact on the microelectronics and information technology industry We highlight and explore four key areas: magnetic memories, magnetic sensors, radio-frequency and microwave devices, and logic and non-Boolean devices We also discuss the challenges—at both the device and the system level—that need be addressed in order to integrate spintronic materials and functionalities into mainstream microelectronic platforms This Review Article examines the potential of spintronics in four key areas of application —memories, sensors, microwave devices, and logic devices — and discusses the challenges that need be addressed in order to integrate spintronic materials and functionalities into mainstream microelectronic platforms

Opportunities and challenges for spintronics in the microelectronics industry

Non-volatile magnetic random-access memories (MRAMs), such as spin-transfer torque MRAM and next-generation spin-orbit torque MRAM, are emerging as key to enabling low-power technologies, which are expected to spread over large markets from embedded memories to the Internet of Things. Concurrently, the development and performances of devices based on two-dimensional van der Waals heterostructures bring ultracompact multilayer compounds with unprecedented material-engineering capabilities. Here we provide an overview of the current developments and challenges in regard to MRAM, and then outline the opportunities that can arise by incorporating two-dimensional material technologies. We highlight the fundamental properties of atomically smooth interfaces, the reduced material intermixing, the crystal symmetries and the proximity effects as the key drivers for possible disruptive improvements for MRAM at advanced technology nodes. 

/pdf/two-dimensional-materials-prospects-for-non-volatile-1uvfiyco.pdf

Two-dimensional materials prospects for non-volatile spintronic memories

Magnetic Random Access Memory (MRAM) is a very promising emerging memory technology because of its various advantages such as nonvolatility, high density and scalability. In particular, Spin Orbit Torque (SOT) MRAM is gaining interest as it comes along with all the benefits of its predecessor Spin Transfer Torque (STT) MRAM, but is supposed to eliminate some of its shortcomings. Especially the split of read and write paths in SOT-MRAM promises faster access times and lower energy consumption compared to STT-MRAM. In this paper, we provide a very detailed analysis of SOT-MRAM at both the circuit- and architecture-level. We present a detailed evaluation of performance and energy related parameters and compare the novel SOT-MRAM with several other memory technologies. Our architecture-level analysis shows that a hybrid -combination of SRAM for the L1-Data-cache, SOT-MRAM for the L1-Instruction-cache and L2-cache can reduce the energy consumption by 60% while the performance increases by 1% compared to an SRAM-only configuration. Moreover, the retention failure probability of SOT-MRAM is $27\boldsymbol {\times }$ smaller than the probability of radiation-induced Soft Errors in SRAM, for a 65nm technology node. All of these advantages together make SOT-MRAM a viable choice for microprocessor caches.

/pdf/evaluation-of-hybrid-memory-technologies-using-sot-mram-for-25n66ktgbr.pdf

Evaluation of Hybrid Memory Technologies Using SOT-MRAM for On-Chip Cache Hierarchy

This paper deals with a new MRAM technology whose writing scheme relies on the Spin Orbit Torque (SOT). Compared to Spin Transfer Torque (STT) MRAM, it offers a very fast switching, a quasi-infinite endurance and improves the reliability by solving the issue of “read disturb”, thanks to separate reading and writing paths. These properties allow introducing SOT at all-levels of the memory hierarchy of systems and adressing applications which could not be easily implemented by STT-MRAM. We present this emerging technology and a full design framework, allowing to design and simulate hybrid CMOS/SOT complex circuits at any level of abstraction, from device to system. The results obtained are very promising and show that this technology leads to a reduced power consumption of circuits without notable penalty in terms of performance.

Ultra-Fast and High-Reliability SOT-MRAM: From Cache Replacement to Normally-Off Computing

A novel nonvolatile flip-flop based on spin-orbit torque magnetic tunnel junctions (SOT-MTJs) is proposed for fast and ultralow energy applications A case study of this nonvolatile flip-flop is considered In addition to the independence between writing and reading paths, which offers a high reliability, the low resistive writing path performs high-speed, and energy-efficient WRITE operation We compare the SOT-MTJ performances metrics with the spin transfer torque (STT)-MTJ Based on accurate compact models, simulation results show an improvement, which attains 20× in terms of WRITE energy per bit cell At the same writing current and supply voltage, the SOT-MTJ achieves a writing frequency 4× higher than the STT-MTJ

Spin Orbit Torque Non-Volatile Flip-Flop for High Speed and Low Energy Applications

MRAM technology provides a combination of fast access time, non-volatility, data retention and endurance. While a growing interest is given to two-terminal Magnetic Tunnel Junctions (MTJ) based on Spin-Transfer Torque (STT) switching as the potential candidate for a universal memory, its reliability is dramatically decreased because of the common writing/reading path. Three-terminal MTJ based on Spin-Orbit Torque (SOT) approach revitalizes the hope of an ideal MRAM. It can overcome the reliability barrier encountered in current two-terminal MTJs by separating the reading and the writing path. In this paper, we study two possible writing schemes for the SOT-MTJ device based on recently fabricated samples. While the first is based on precessional switching, the second requires the presence of permanent magnetic field. Based on an accurate Verilog-A model, we simulate the two writing techniques and we highlight advantages and drawbacks of each one. Using the second technique, pioneering logic circuits based on the three-terminal architecture of the SOT-MTJ described in this work are under development with preliminary attractive results. Keywords—Spin orbit Torque, Magnetic Tunnel Junction, MRAM, Spintronic, Circuit simulation.

/pdf/study-of-two-writing-schemes-for-a-magnetic-tunnel-junction-3j6vnaoxcs.pdf

Study of Two Writing Schemes for a Magnetic Tunnel Junction Based On Spin Orbit Torque

Magnetic random access memory based on magnetic tunnel junctions (MTJs) is among the most attractive technologies of emerging non-volatile memories. However, the integration of spin-based devices in integrated circuits is still hindered by a lack of established standard electrical simulator models. Many of such models have been proposed during the past decade which can be classified into two categories: the first ones are based on the physical Landau-Lifshitz-Gilbert (LLG) equation describing real-time MTJ magnetic switching dynamics; the second one uses analytical expressions for switching thresholds derived from the LLG equation. The aim of this reported work was to investigate for the first time the capability of each strategy to fulfil the need of industrial standard electrical simulation tools and pave the path towards a standard industrial model. Multi-simulator compatibility, efficient runtime, accuracy and reliability are the three main assets of a device model. It is shown that using the Cadence® tools suite with the Spectre® simulator, the LLG modelling strategy overcomes the analytical approach in terms of accuracy and speed with a 7× faster runtime. Both models require nearly the same hardware memory resources.

Comparison of Verilog-A compact modelling strategies for spintronic devices

The spin-orbit-torque magnetic tunnel junction (SOT-MTJ) is a promising device for data storage. Most of the issues encountered with scalable spin transfer-torque (STT) devices are visibly moved. Thanks to a three-terminal architecture, the reliability is increased by separating the read and the write paths. Furthermore, SOT-induced magnetisation switching can be very fast, thanks to a low-resistive writing path. The writing operation is symmetrical. Thus, it requires the same current density to switch between the parallel and antiparallel states. All these advantages make the SOT-MTJ device an ultimate candidate for introducing non-volatility in ultra-fast and power-efficient integrated circuits. A mixed CMOS/magnetic non-volatile flip-flop (NVFF) is described. The proposed architecture offers the possibility to use the usual CMOS flip-flop functionality with possible magnetic data store and restore operations while keeping non-volatility when the circuit is powered off. With a 135 nm dimension, the SOT-MTJ-based NVFF demonstrated a very high switching with a 5× decrease in terms of writing energy/bit when compared with an STT device.

Ultra-energy-efficient CMOS/magnetic non-volatile flip-flop based on spin-orbit torque device

Since the advent of the MOS transistor, the performance of microelectronic circuits has followed Moore’s law, stating that their speed and density would double every 18 months. Today, this trend tends to get out of breath: the continuously decreasing size of devices and increasing operation frequency result in power consumption and heating issues. Among the solutions investigated to circumvent these limitations, the use of non-volatile devices appears particularly promising. It allows easing, for example, the power gating technique, which consists in cutting-off the power supply of inactive blocks without losing information, drastically reducing the standby power consumption. In this approach, the advantages of magnetic tunnel junctions (MTJs) compared with other non-volatile devices allow one to design hybrid CMOS/magnetic circuits with high performance and new functionalities. Designing such circuits requires integrating MTJs in standard microelectronics design suites. This is performed by means of a pr...

A hybrid magnetic/complementary metal oxide semiconductor process design kit for the design of low-power non-volatile logic circuits

This paper addresses the power reduction techniques for the ultra-low power integrated circuits. We propose to implement non-volatile asynchronous circuits which will have a quasi-zero leakage consumption, almost instant back-up and wake-up time and will be robust to unstable supply environments. This paper presents the implementation of the non-volatile C-element and Half-Buffer, based on hybrid technology incorporating 28nm CMOS FD-SOI and 40nm STT-MRAM magnetic technologies. We discuss our recent simulation results of the proposed non-volatile blocks and as well more complex structures based on them. We derive the criteria of the implementation efficiency and compare the conventional asynchronous blocks with the proposed non-volatile ones.

Non-volatility for Ultra-Low Power Asynchronous Circuits in Hybrid CMOS/Magnetic Technology

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