Fabrice Bernard-Granger
University of Grenoble
7 Papers
15 Citations
Fabrice Bernard-Granger is an academic researcher from University of Grenoble. The author has contributed to research in topics: Magnetoresistive random-access memory & Non-volatile memory. The author has an hindex of 3, co-authored 7 publications. Previous affiliations of Fabrice Bernard-Granger include Alternatives.
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Papers
Spin Orbit Torque Non-Volatile Flip-Flop for High Speed and Low Energy Applications
TL;DR: In this article, a spin-orbit torque magnetic tunnel junctions (SOT-MTJ) was proposed for fast and ultralow energy applications, which offers high speed and energy-efficient write operation.
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Comparison of Verilog-A compact modelling strategies for spintronic devices
TL;DR: It is shown that using the Cadence® tools suite with the Spectre® simulator, the LLG modelling strategy overcomes the analytical approach in terms of accuracy and speed with a 7× faster runtime.
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Reducing System Power Consumption Using Check-Pointing on Nonvolatile Embedded Magnetic Random Access Memories
Christophe Layer,Laurent Becker,Kotb Jabeur,Sylvain Claireux,Bernard Dieny,Guillaume Prenat,Gregory Di Pendina,Stéphane Gros,Pierre Paoli,Virgile Javerliac,Fabrice Bernard-Granger,Loic Decloedt +11 more
TL;DR: This work develops a fully characterized system-on-chip from the basic cell up to the system architecture in a 40nm LP hybrid CMOS/magnetic process and implements a check-pointing methodology based on the regular interrupt routines of a processor to enable a fast power on and off functionality.
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Hybrid STT/CMOS Design of an Interrupt Based Instant On/Off Mechanism for Low-Power SoC
Christophe Layer,Kotb Jabeur,Laurent Becker,Bernard Dieny,Stéphane Gros,Virgile Javerliac,Pierre Paoli,Fabrice Bernard-Granger +7 more
- 08 Jul 2015
TL;DR: The design and the evaluation of a low-power System-on-Chip in an advanced hybrid 40nm magnetic/CMOS technology node with embedded NVM (Non-Volatile Memory) improves the whole system in terms of power consumption and functionality enhancements, compared to an equivalent system relying on standard volatile memory blocks only.
3
Low-power hybrid STT/CMOS system-on-chip embedding non-volatile magnetic memory blocks
Christophe Layer,Kotb Jabeur,Stéphane Gros,Laurent Becker,Pierre Paoli,Fabrice Bernard-Granger,Virgile Javerliac,Bernard Dieny +7 more
- 07 Jun 2015
TL;DR: This paper describes a fully embedded System-on-Chip (SoC), i.e., without external memory interface, and discusses the benefits of embedding NVM elements into the system in terms of power consumption and functionality enhancements compared to an equivalent system relying on standard volatile memory blocks.
3