Abstract: The embodiments herein describe a memory device and method for reading and writing data. In one embodiment, a memory device is provided comprising a memory array and first and second data buffers in communication with the memory array. The second data buffer comprises a larger storage capacity than the first data buffer. During a write operation, data is stored in the second data buffer and then stored in the memory array. During a read operation, data is read from the memory array and then stored in the first data buffer but not in the second data buffer. Because the smaller-storage-capacity buffer takes less time to fill than the larger-storage-capacity buffer, there is less of a delay in outputting data from the memory device as compared to memory devices that use a larger-storage-capacity buffer for both read and write operations. Other embodiments are provided, and each of the embodiments can be used alone or in combination with one another.

Abstract: An analog storage flash memory by which sufficient write accuracy can be obtained even when the write speed of the memory cell transistor disperses due to manufacturing dispersion or other reasons. A read voltage adjustment circuit outputs the read voltage generated by a read voltage generation circuit as is, or drops and outputs the read voltage. A write voltage adjustment circuit outputs the write voltage generated by a write voltage generation circuit as is, or drops and outputs the write voltage. A write control circuit repeats the write operation at the write voltage Vw until the memory cell transistor turns OFF at the read voltage Vr-ΔVr in the first write cycle, and repeats the write operation at the write voltage Vw-ΔVw until the memory transistor turns OFF at the read voltage Vr in the second write cycle.

Abstract: A method for managing read and write data congestion in a system for executing write and read data commands and having a buffer pool of blocks for temporarily storing read and write data is disclosed. Management of the buffer pool and the initiation of read and write commands ensures that free blocks are available to temporarily store read data arriving at a host bus adapter (HBA). If the currently available blocks would be substantially consumed by the total outstanding inbound read data requested, no more write data commands will be initiated. As inbound read data is received into the buffer pool and subsequently transferred out of the buffer pool to the initiator device, the blocks in the buffer pool are freed up. When the read data transfer is completed and sufficient buffer resources have been freed up, read and write data commands may resume.

Abstract: Disclosed is a method and system for performing periodic replication using a write-ordered log. According to one embodiment, a plurality of write operations to a primary data volume are tracked using a write operation log and then data associated with the plurality of write operations is replicated to a secondary data volume by coalescing the plurality of write operations utilizing the write operation log and transferring data associated with the plurality of write operations to the secondary data volume. According to another embodiment the described tracking includes storing metadata associated with the plurality of write operations within the write operation log. In another embodiment, the described coalescing includes identifying a non-overlapping portion of a first write operation and a second write operation of the plurality of write operations utilizing the metadata.

Abstract: Conductive memory array having page mode and burst mode read capability. The conductive memory array includes two-terminal memory plugs and sensing circuits configured to read information from the memory plugs in two cycles. The array also includes associated circuitry that allows it to carry out such two-cycle reads in either page mode or burst mode.

Abstract: A system and method are disclosed for improving the efficiency of write operations by intelligently managing disk pages that are written during checkpoint operations so that write operations can occur with reduced numbers of writes. As write data is received and cached, for example, by a database application, disk pages are allocated to the write data. When a checkpoint operation is taken to write the data cache to disk as modifications or additions to the database file, an intelligent write management module re-assesses the disk page allocation and re-maps disk writes to improve the efficiency of disk input/output (I/O) operations. As such, significant improvements in the speed and efficiency of database operations during checkpoint events are achieved.

Abstract: A method and apparatus for flushing a write cache includes receiving a read or a write storage request, determining whether the storage request comprises a full or partial hit with data stored in a write cache one or more lines, some of which may be dirty. If the hit is partial and the one or more lines of the data are dirty, flushing the dirty data. If the hit is full or partial and any of the write cache lines are not dirty, and the storage request is a write request, flushing the dirty write cache lines, invalidating the non dirty write cache line, writing the storage request data into the write cache as a new write cache line and marking the new write cache line dirty. If the hit is full, all write cache lines are marked dirty, and the storage request is a write request, overlaying the cache write line with the storage request data and marking the write cache line as dirty.

Abstract: A nonvolatile semiconductor memory is disclosed, which comprises a nonvolatile memory cell array, a write circuit which repeatedly executes a write and a verification, and a write voltage control circuit, the write voltage control circuit comprising a first binary counter which counts a first clock signal supplied every time the verification fails and supplies output data to the write circuit, a first register which stores data for setting the number of erases and verifications, a second binary counter which is reset using a first timing, counts a second clock signal supplied if a verify write executed on the target write unit fails, an accumulative value storage circuit which is reset using a second timing and stores a value corresponding to an accumulative value for the contents of the second binary counter, and a nonvolatile storage element which stores the appropriate value for the write start voltage.

Abstract: In a semiconductor memory device in which a system clock that is supplied from the outside and a data strobe signal that is received as input and supplied as output in synchronization with data are used to control operations for reading and writing data, the transmission of write data from FIFO memories to write amplifiers is controlled by the data strobe signal. In addition, switches for connecting write amplifiers with bit lines that are linked to memory cells that correspond to addresses to which write data are to be written are driven without delaying with respect to a timing signal that is synchronized with the system clock. Write data that have been received as burst input are transmitted in parallel from the FIFO memories to the write amplifiers in units of the prefetch number.

Abstract: In a memory card which includes a memory chip and a controller connected to the memory chip for the control of transferring a data from outside, the controller is provided with a buffer in which data is temporarily stored. In a first operation mode, the controller clears the data stored in the buffer after the data in the buffer is transferred to the memory chip. In a second operation mode, the controller does not clear the data stored in the buffer even after the data in the buffer is transferred to the memory chip. By the use of these modes, it becomes possible to write the data obtained by means of external transfer into the memory chip repeatedly for a plurality of times by means of internal transfer. Thus, it becomes unnecessary to repeat external transfer and internal transfer every time.

Abstract: A semiconductor storage apparatus such as a disk pack in which a controller sends a second write command or instruction while a write operation for a first write command or instruction is being carried out. The storage apparatus includes a plurality of flash memories which operate slower in writing data thereinto than the reading data therefrom, a write buffer memory in which data are temporarily held, a processor which controls the data writing operation and which transfers and analyzes commands and statuses, an address controller which generates physical addresses, a circuit which generates a writing supply voltage Vpp for the flash memories, a memory address bus, and a data bus. The semiconductor disk pack is connected to a standard bus in a personal computer or the like. The processor writes the data of one word into a desired one of the flash memories, and it continuously writes the data of one word into an accessible one of the other flash memories during a latency which extends until the desired flash memory becomes capable of writing the next data of one word thereinto.

Abstract: A batched, asynchronous data redundancy technique. A sequence of write transactions are performed at a first storage facility. The write transactions are arranged into a sequence of send batches forwarded to a second storage facility where the write transactions are arranged into a sequence of receive batches. At the first storage facility or at the second storage facility, a first write transaction is replaced with a second write transaction wherein the second write transaction overwrites data written by the first write transaction. A receive batch includes all write transactions between the first write transaction and the second write transaction. The write transactions are applied to a redundant data copy at the second storage facility in which all of the write transactions for the receive batch are applied as a whole to the redundant copy of the data.

Abstract: A method of writing data to a storage medium comprises receiving blocks of data to be written to a physical medium of the disk, from a data source and storing the blocks of data in a write cache for the disk. The method further comprises checking the status of a flush criterion that controls when to flush the write cache; flushing the write cache by writing the data in the write cache to the physical medium if the flush criterion is satisfied; and sending a message to the data source to indicate that the blocks of data have been written to the physical medium.

Abstract: A method for recovering dirty write cache data after controller power loss or failure from one of two independently battery backed up and mirrored write caches. Two independent controllers jointly operate with a permanent data storage system. Each controller has a write cache that is a mirror of the write cache in the other controller. The primary controller resets a power down flag stored each write cache upon proper shutdown. The primary controller further increments and stores a configuration sequence number into each write cache upon proper shutdown. If a primary controller powers up and identifies that the write cache was not properly shutdown due to the state of the power down flag, it flushes the dirty data in the write cache only if the configuration sequence number contained in the write cache is the same as the configuration sequence number contained in the primary controller. If the configuration sequence number in the primary controller is higher than the configuration sequence number in the write cache, the dirty data was previously flushed to permanent data storage with the other write cache.

Abstract: A method of and apparatus for handling errors occurring in data stored in memory is presented. Data to be stored in a buffer memory is applied to a generator matrix to generate parity check bits. The parity check bits are stored in the buffer memory along with the data. The stored data and parity check bits are read and the read data is used to regenerate the parity check bits. A result produced from the stored and regenerated parity check bits is usable to directly identify a location of an erroneous bit of the data in the buffer memory.

Abstract: A memory module includes a memory hub coupled to several memory devices. The memory hub includes a posted write buffer that stores write requests so that subsequently issued read requests can first be coupled to the memory devices. The write request addresses are also posted in the buffer and compared to subsequent read request addresses. In the event of a positive comparison indicating that a read request is directed to an address to which an earlier write request was directed, the read data are provided from the buffer. When the memory devices are not busy servicing read request, the write requests can be transferred from the posted write buffer to the memory devices. The write requests may also be accumulated in the posted write buffer until either a predetermined number of write requests have been accumulated or the write requests have been posted for a predetermined duration.

Abstract: According to one aspect of the invention, a method is provided in which one or more write commands and their corresponding write data are received from a first device. The corresponding write data may be delayed by the first device by a first delay period. The one or more write commands and their corresponding write data are stored in a set of buffers. In response to another write command being received from the first device, a buffered write command and its corresponding write data are sent to a second device for execution, without waiting for the write data corresponding to said another write command to be sent from the first device.

Abstract: A variable latency elastic buffer comprises a plurality of memory locations in which to hold data. A write and read pointer may point to respective write and read addresses of the plurality of locations in which to write and read data. A controller may hold or increment the address of the read pointer upon determining that the amount of data within the buffer differs from a nominal fill level. In a particular embodiment, initialization circuitry may be operable to initialize the read and write addresses of the respective pointers responsive to an initialization request. The read and write addresses may differ from one another by an offset value equal to a value programmed for the nominal value.

Abstract: An optical drive writes information to an optical medium by obtaining a write strategy for the optical medium from a write strategy table embedded in the optical medium. A write module in the optical drive reads an optical drive identification code from the optical medium to select a write strategy associated with the optical drive. The write strategy of the embedded write strategy table that is identified for the optical drive is retrieved by the write module to write information to the optical medium with the optical drive using the identified write strategy. In one embodiment, a time stamp of the identified write strategy retrieved from the optical medium is compared with a time stamp of a write strategy already available to the optical drive to select the most recent write strategy for use by the optical drive. The write strategy table is embedded in the optical medium at manufacture of the optical medium, such as by stamping or burning the data into the optical material of the optical medium.

Abstract: A graphics system may include a frame buffer and a hardware accelerator. The frame buffer may include a sample buffer and a double-buffered display area. The hardware accelerator may be coupled to the frame buffer, and configured (a) to receive primitives, (b) to generate samples for the primitives based on a dynamically adjustable sample density value, (c) to write the samples into the sample buffer, (d) to read the samples from the sample buffer, (e) to filter the samples to generate pixels, (f) to store the pixels in a back buffer of the double-buffered display area. A host computer may be configured (e.g., by means of stored program instructions) to dynamically update programmable registers of the graphics system to reallocate the sample buffer in the frame buffer in response to user input specifying a change in one or more window size parameters.

Abstract: Provided are a method, system, and program for mirroring data. A relationship is established between a plurality of source data units in a primary storage and a plurality of corresponding target data units in a secondary storage. An operation is initiated to perform an initial copy of all source data units in the relationship to the corresponding target data units. An update is received to a source data unit and a determination is made of whether a first write mode is indicated. The update is copied to the source data unit in the first write mode to the corresponding target data unit if the first copy write is indicated. Otherwise, the update is copied to the source data unit corresponding target data unit in a second write mode if the first write mode is not indicated. If the first write mode is not indicated, then a determination is made of whether a number of writes for all data units subject to the relationship falls below a threshold and the first write mode is indicated if the number of writes for all data units subject to the relationship falls below the threshold.

Abstract: A memory system having a memory controller and a memory device coupled to the memory controller. The memory controller outputs a write data value to the memory device. The memory device receives the write data value from the memory controller, and compares the write data value with a mask key value. If the write data value matches the mask key value, the memory device does not store the write data value. If the write data value does not match the mask key value, the memory device stores the write data value.

Abstract: A logic circuit operates write receivers in a dynamic random access memory device in either a low-power mode, high write latency mode or a high-power mode, low write latency mode The logic circuit receives a first signal indicative of whether the high-power, low write latency mode has been enabled, a second signal indicative of whether a row of memory cells in the memory device is active, a third signal indicative of whether the memory device is being operated in a power down mode, and a fourth signal indicative of whether read transmitters in the memory device are active The logic circuit maintains power to the write receivers whenever the high-power, low write latency mode has been enabled if a row of memory cells in the memory device is active, the memory device is not being operated in the power down mode, and the read transmitters in the memory device are not active

Abstract: A novel storage format enabling a method for improved memory management of video images is described The method includes receiving an image consisting of a plurality of color components Once received, the plurality of color components is converted to a mixed format of planar format and packed format The mixed packet format is implemented by storing one or more of the plurality of color components in a planar format and storing one or more of the plurality of color components in a packed format A method for writing out video images is also described utilizing a write combining (WC) fame buffer The decoding method motion compensates groups of macroblocks in order to eliminate partial writes from the WC frame buffer

Abstract: A bridge for interconnecting a processor to a peripheral device by way of a PCI bus may have a read buffer. The bridge autonomously requests data from the peripheral device and places received data in the read buffer. The processor reads the data from the receive buffer. The bridge may have a write buffer. The bridge accumulates data in the write buffer until a triggering event occurs. Upon the occurrence of a triggering event the bridge sends the data in the receive buffer to the peripheral device in a burst.

Abstract: A read/write scheduling apparatus of controller chip and method for the same. The read/write scheduling apparatus is used for arbitrating a plurality of read and write requests from a CPU to access a memory unit. The read request has higher priority in a host bandwidth limited case and the write requests in write queues are not sent until a predetermined amount of write requests are accumulated. In a DRAM bandwidth limited case, the read and the write requests have the same priority. The scheduling apparatus counts the number of the read and write requests to the memory unit within a predetermined time, the operation is changed to DRAM bandwidth limited case in case that the counted number is larger than a predetermined number.

Abstract: A variable depth write data buffer is provided in a memory device coupled to a master device by an interconnect structure in an embodiment of the present invention. The variable depth write data buffer reduces a delay, or W-R turnaround bubble, time between a read operation and a write operation of a memory device memory core. The variable depth write buffer is programmable to store 1 to 4 data packets in an embodiment of the present invention. The variable depth write data buffer may also be programmed for multiple memory device configurations. A method preloads write data without address information into a write data buffer and a subsequent WRITE command causes the previously loaded write data to be retrieved from the write data buffer and written to a memory core according to an embodiment of the present invention.

Abstract: Techniques are described for accurately and efficiently emulating an instruction processor having a write buffer. The described techniques may be utilized to quickly develop an emulated instruction processor that provides a fully-functional write buffer interface in an efficient and elegant manner. For example, a system is described that includes a computing system that provides an emulation environment, and software executing within the emulation environment that emulates an instruction processor having a write buffer interface and a memory interface. The software emulates the instruction processor by selectively outputting a write request on the write buffer interface or the memory interface in response to an emulation control instruction embedded within an instruction stream.

Abstract: A technique enhances a write data path within a storage operating system executing on a storage system. As used herein, the write data path defines program logic used by a file system of the storage operating system to process write requests directed to data served by the file system. The technique enhances the write data path of the storage system by providing a “zero copy” write data path embodied as a function of the storage operating system that eliminates a copy operation for a write request received at the storage system. The eliminated operation is a data copy operation from a list of input buffers to buffers used by the file system.