Source-synchronous

Abstract: A 15-Mbps, single-channel wireless source synchronous (SWSS) transceiver with a 1-mm on-chip integrated loop antenna has been developed in 90-nm CMOS for 1.25-cm ‘touch-and-proceed communication’ between electronic devices. A newly developed FDM-based SWSS architecture makes simultaneous CLOCK and DATA transmission possible with only a single antenna as well as the elimination of PLL and clock recovery blocks in Rx. We have successfully demonstrated a 1.0-cm robust alignment of antenna position for 1.0-cm communication distance with a 1-mm on-chip antenna at BER<10−5. Additionally, we have successfully demonstrated 20-Mbps transmission of 5-mm distance at BER<10−3.

Abstract: This paper presents a source-synchronous receiver architecture for use in parallel optical links. The proposed system is reconfigurable, allowing any channel to be used as a clock or data lane. The architecture is designed for mode-division multiplexed (MDM) optical links with forwarded clocks and allows the sensitive clock signal to be placed in the lane with the least amount of optical crosstalk for a given photonic interconnect. This configurability, which accounts for variation in integrated optics by leveraging the more robust electronic chip, optimizes the performance in electronic/optic codesigned solutions and may improve the yield. The architecture contains a dynamic clock distribution network, able to send a reference clock signal from the chosen clock receiver to any other data-configured receiver. The proposed architecture has been implemented on an experimental chip consisting of two receivers designed in the 65-nm CMOS technology. Electrical measurements at 8 Gb/s were done, and bit error rate curves are presented. They demonstrate the ability to swap and repurpose the clock and data inputs between the receivers, with similar sensitivity upon reconfiguration as a proof of concept.

Abstract: The invention provides a field-programmable gate array (FPGA) prototype verification clock device, and relates to the field of FPGA prototype verification. The device comprises a master control chip, a first FPGA chip, a second FPGA chip, an external clock input/output circuit which is connected with the first FPGA chip and the second FPGA chip simultaneously, an internal programmable clock circuit of which one end is connected with the master control chip and the other end is connected with the first FPGA chip and the second FPGA chip respectively, an external direct-insert crystal oscillator circuit which is directly connected with the first FPGA chip or the second FPGA chip or the first FPGA chip and the second FPGA chip simultaneously, a source synchronous clock circuit which points from the first FPGA chip to the second FPGA chip, and/or a source synchronous clock circuit which points from the second FPGA chip to the first FPGA chip, and a feedback clock circuit which is used for introducing the feedback clock of the first FPGA chip or the second FPGA chip into the master control chip and introducing the adjusted clock into the first FPGA chip and the second FPGA chip. The device realizes the centralized management of various clocks and maximizes a system clock resource utilization rate.

Abstract: A simultaneous bidirectional (SBD) transceiver employs an efficient voltage-mode driver with a resistor-transconductance (R-gm) hybrid to enable transmission and reception of data on a single differential channel at the same time. An FIR filter-based adaptive echo cancellation system that cancels both near-end and far-end echoes allows for the support of a wide range of channels, while a continuous-time linear equalizer efficiently compensates for channel loss. The quarter-rate source-synchronous transceiver utilizes a 5/4X phase interpolator-based clock and data recovery system to set the optimum data sampling point. Fabricated in 28nm CMOS, the 32Gb/s SBD transceiver achieves 1.83mW/Gb/s and compensates for up to 10.2dB loss.