Abstract: A Green NAND SSD Driver (GNSD) driver executes on a host to increase data-retention of flash memory attached to a Super Enhanced Endurance Device (SEED) or Solid-State Drive (SSD). Host accesses to flash are intercepted by the GNSD driver using upper and lower-level filter drivers. A retention-check timer causes a retention routine to be periodically executed. The routine sends high-level commands to the SEED that causes the SEED to refresh either all data or just data blocks with older write dates. Data is refreshed by moving to a new physical block. The retention routine can track write dates of logical blocks and command a SSD to move logical blocks with older write dates. A retention card has a controller that performs the retention routine when not connected to a host, while a SEED power card allows the SEED to refresh data when no host is attached to the SEED.

Abstract: Methods, systems, and computer readable media for providing a flexible host memory buffer are disclosed. One method includes allocating an amount of host memory as a host memory buffer accessible by a solid state drive (SSD) as a cache for SSD data. The method further includes caching data from the solid state drive in the host memory buffer. The method further includes monitoring utilization of the host memory buffer. The method further includes dynamically increasing or decreasing the amount of host memory allocated for the host memory buffer based on the utilization.

Abstract: Embodiments of the inventive concept include solid state drive (SSD) multi-card adapters that can include multiple solid state drive cards, which can be incorporated into existing enterprise servers without major architectural changes, thereby enabling the server industry ecosystem to easily integrate evolving solid state drive technologies into servers. The SSD multi-card adapters can include an interface section between various solid state drive cards and drive connector types. The interface section can perform protocol translation, packet switching and routing, data encryption, data compression, management information aggregation, virtualization, and other functions.

Abstract: Virtualization has become one of the most helpful techniques, and today it is prevalent in several computing environments including desktops, data-centers, and enterprises. However, an I/O scalability issue in virtualized environments still needs to be addressed because I/O layers are implemented to be oblivious to the I/O behaviors on virtual machines (VM). In particular, when a multi-queue solid state drive (SSD) is used as a secondary storage, each VM reveals semantic gap that degrades the overall performance of the VM by up to 74%. This is due to two key problems. First, the multi-queue SSD accelerates the possibility of lock contentions. Second, even though both the host machine and the multi-queue SSD provide multiple I/O queues for I/O parallelism, existing Virtio-Blk-Data-Plane supports only one I/O queue by an I/O thread for submitting all I/O requests. In this paper, we propose a novel approach, including the design of virtual CPU (vCPU)-dedicated queues and I/O threads, which efficiently distributes the lock contentions and addresses the parallelism issue of Virtio-Blk-Data-Plane in virtualized environments. We design our approach based on the above principle, which allocates a dedicated queue and an I/O thread for each vCPU to reduce the semantic gap. We also implement our approach based on Linux 3.17, and modify both the Virtio-Blk frontend driver of guest OS and the Virtio-Blk backend driver of Quick Emulator (QEMU) 2.1.2. Our experimental results with various I/O traces clearly show that our design improves the I/O operations per second (IOPS) in virtualized environments by up to 167% over existing QEMU.

Abstract: In this paper, we propose a new I/O scheduler for SSDs, called Amphibian, which exploits the up-level request characteristics and the low-level internal parallelism of flash chips to improve the performance of SSD-based storage systems. Amphibian includes two parts: the size-based request ordering that gives higher priority to first processing the small requests and the Garbage Collection (GC) aware request dispatching that avoids issuing requests to the flash chips that are in the GC state. By first processing the small requests and avoiding issuing the GC-conflict requests in the I/O waiting queue, the average waiting times of the requests are reduced significantly. The extensive evaluation results show that compared with existing I/O schedulers, Amphibian improves the throughput and the average response times significantly. Consequently, the I/O performance of the SSD-based storage systems is improved.

Abstract: Hybrid parallel file systems (PFS), consisting of multiple HDD and SSD I/O servers, provide a promising design for data intensive applications. The efficiency of a hybrid PFS relies on the file's data layout. However, most current layout strategies are designed and optimized for homogeneous servers. Using them directly in a hybrid PFS neither addresses the heterogeneity of servers nor the varying access patterns of applications, making hybrid PFSs disappointingly inefficient. In this paper, we propose HAS, a novel heterogeneity-aware selective data layout scheme for hybrid PFSs. HAS alleviates the inter-server load imbalance through skewing data distribution on heterogeneous servers based on their storage performance. To largely improve the entire system's I/O efficiency, HAS adaptively selects the optimal data layout from three typical candidates according to the application's data access patterns, based on a newly developed selection and distribution algorithm. We have implemented HAS within OrangeFS to provide efficient data distribution for data-intensive applications. Our extensive experiments validate that HAS significantly increases the I/O throughput of hybrid PFSs, compared to existing data layout optimization methods.

Abstract: Methods and systems are presented for allocating CPU cycles among processes in a storage system. One method includes operations for maintaining segments in a first memory, each segment including blocks, and for maintaining a block temperature for each block in a second memory. The first memory is a read-cache where one segment is written at a time, and each block is readable from the first memory without reading the corresponding complete segment. The block temperature is based on the frequency of access to the respective block, and a segment temperature is based on the block temperature of its blocks. Additionally, the segment with the lowest segment temperature is selected for eviction from the second memory, and blocks in the selected segment with a block temperature greater than a threshold temperature are identified. The selected segment is evicted, and a segment with the identified blocks is written to the first memory.

Abstract: Performance isolation is critical in shared storage systems, a popular storage solution In a shared storage system, interference between requests from different users can affect the accuracy of I/O cost accounting, resulting in poor performance isolation Recently, NAND flash-memory-based solid-state drives (SSDs) have been increasingly used in shared storage systems However, interference in SSD-based shared storage systems has not been addressed In this article, two types of interference, namely, queuing delay (QD) interference and garbage collection (GC) interference, are identified in a shared SSD Additionally, a framework called VSSD is proposed to address these types of interference VSSD is composed of two components: the FACO credit-based I/O scheduler designed to address QD interference and the ViSA flash translation layer designed to address GC interference The VSSD framework aims to be implemented in the firmware running on an SSD controller With VSSD, interference in an SSD can be eliminated and performance isolation can be ensured Both synthetic and application workloads are used to evaluate the effectiveness of the proposed VSSD framework The performance results show the following First, QD and GC interference exists and can result in poor performance isolation between users on SSD-based shared storage systems Second, VSSD is effective in eliminating the interference and achieving performance isolation between users Third, the overhead of VSSD is insignificant

Abstract: A solid state drive has a power failure savings mode that permits a reduction in holdup time for a temporary backup power supply. The solid state drive stores data in a multi-level cell (MLC) mode. In a power fail saving mode system metadata is written in a pseudo Single Level Cell (pSLC) mode. In the normal operating mode page writes are performed in complete blocks. In the power fail save saving mode data from a write buffer is written and additional dummy pages written to reduce the total number of pages that must be written to below a complete block size with the dummy pages providing protection from data corruption.

Abstract: Parallel file systems (PFS) are commonly used in high-end computing systems. With the emergence of solid state drives (SSD), hybrid PFSs, which consist of both HDD and SSD servers, provide a practical I/O system solution for data-intensive applications. However, most existing PFS layout schemes are inefficient for hybrid PFSs due to their lack of awareness of the performance differences between heterogeneous servers and the workload changes between different parts of a file. This lack of recognition can result in severe I/O performance degradation. In this study, we propose a heterogeneity-aware region-level (HARL) data layout scheme to improve the data distribution of a hybrid PFS. HARL first divides a file into fine-grained, varying sized regions according to the changes of an application's I/O workload, then chooses appropriate file stripe sizes on heterogeneous servers based on the server performance for each file region. Experimental results of representative benchmarks show that HARL can greatly improve the I/O system performance.

Abstract: Embodiments of the inventive concept include 25 inch hard disk drive form factor solid state drive multi-card adapters that can include multiple M2 solid state drive cards, which can be incorporated into existing enterprise servers without major architectural changes, thereby enabling the server industry ecosystem to easily integrate M2 solid state drive technology into servers Multiple M2 solid state drive cards and a peripheral component interconnect express (PCIe) switch can be included within a 25 inch hard disk drive form factor solid state drive multi-card adapter The solid state drive multi-card adapters can be attached to or seated within drive bays of a computer server that supports non-volatile memory express (NVMe) 25 inch drives without any changes to the server architecture, thereby providing a straight-forward upgrade path

Abstract: A system and method are disclosed for incorporating mathematical and/or logical functionality within a memory system (such as a solid state drive (SSD)). The mathematical and/or logical functionality may comprise an arithmetic logic unit (ALU). The ALU may be resident in one or both of flash memory chips or the SSD controller. When resident in the flash memory chips, a single ALU or multiple ALUs may be used. For example, a single ALU may be assigned to one, some, or each block of flash memory within the flash memory chip. As another example, an ALU may be assigned to a sub-block construct, such as to each bit line in the block. Having ALUs resident in the SSD enables more processing to be performed within the SSD and reduces the need to transmit data outside of the SSD for processing.

Abstract: In a non-volatile memory such as a NAND flash memory, notification of an area that is no longer needed is provided by a TRIM command, and deletion of the unneeded area is executed by garbage collection. The TRIM command and execution of the garbage collection are detected, and notification thereof is provided, whereby the user can confirm that the data on a solid state drive is invalidated.

Abstract: NAND flash memory has been widely used as a storage device for embedded systems because of its fast access speed, low power consumption, and lower noise compared to a hard disk. However, due to its unique characteristics such as the lack of an in-place update and asymmetric operation speed/unit, conventional disk-based systems and applications may experience severe performance degradation when NAND flash memory is used. When a disk-based index structure such as a B-Tree is implemented in flash memory-based storage systems, intensive overwrite operations, which are caused by record insertion, deletion, and reorganization, may result in severe performance degradation. Although several index structures have been proposed to overcome this problem, they suffer from frequent node splits, rapid increments of tree height, and poor space usage. In this paper, we propose a log-structured B-Tree index structure where a log node corresponding to a leaf node is allocated for updating the modified data, and then these data in the log node are stored in a single write operation. Our proposed index structure reduces additional write operations by deferring parent node changes. In addition, the index structure reduces the number of write operations by directly switching the log node to a leaf node if the data are sequentially inserted according to key order. Through various experiments, we show that our proposed index structure performs better than related techniques.

Abstract: The invention discloses a hybrid memory control method which is applied to each HDD (Hard Disk Drive) memory device and each SSD (Solid State Drive) memory device of a memory system provided with one or a plurality of HDD memory devices and one or a plurality of SDD memory devices, each HDD memory device is connected with the corresponding SSD memory device in the memory system, and each HDD memory device and each SSD memory device are internally and respectively provided with one or a plurality of data blocks The method comprises the steps of periodically acquiring the access information of each data block stored in the memory device; and adjusting the memory position of each data block in the memory system according to the access information of each data block By adopting the technical scheme of the hybrid memory control method provided by the invention, the memory positions of the data blocks can be dynamically configured according to the access frequency, so as to make the best of the advantages of different memory devices

Abstract: Emerging Non-Volatile Memory (NVM) technology with high throughput and scalability has considerable attraction in cloud and enterprise storage systems. The industry and academic communities made the NVMe specification to elicit the highest performance on NVM devices. While the technology is commercially viable, it is important to consider the performance of NVM devices with NVMe specification according to different I/O configurations and analyze workloads on the storage to exploit better performance. This paper presents the features and results of our performance study on a recent NVM express solid state drive (NVMe SSD) developed by Samsung electronics. It is a flash-based PCIe attached SSD built to follow NVMe specification. The maximum throughput is 2.5GB/s and 800MB/s for reading and writing 4KB, respectively. We analyze the performance of NVMe SSD in terms of different performance metrics with microbenchmarks and database workloads.

Abstract: Embodiments of the inventive concept include Open Cloud Server (OCS)-compliant and other enterprise servers having high-density modular non-volatile flash memory blades and associated multi-card modules. A modular non-volatile flash memory blade can be seated within a 1U tray. The flash memory blade can include a server motherboard and multiple non-volatile flash memory blade multi-card modules. Each of the multi-card modules can include a printed circuit board, a switch coupled to the printed circuit board, a module power port, an input/output port, and riser card slots to receive solid state drive riser cards. The solid state drive riser cards can be seated within a corresponding riser card slot of the multi-card modules, and can each include multiple solid state drive chips. The server motherboard can communicate with the solid state drive chips via the cable connector riser cards and associated cables. The switch can expand each upstream port to multiple downstream ports associate with the solid state drive chips.

Abstract: Write buffering not only enables Solid State Drive (SSD) to immediately respond to the write request but also increases the lifespan of the SSD by reducing the amount of data written to the flash memory. However, since the DRAM which is used as a write buffer is volatile, it has a few critical problems such as buffered data loss upon sudden power-off and limited write reduction effect due to the flush commands and synchronous writes from the file system. These problems can be addressed when non-volatile memory (NVRAM) is used, instead of DRAM, as a write buffer. In this paper, we propose a novel Dual-Region Write Buffering (DRWB) scheme that implements logically non-volatile write buffer using large sized DRAM and small capacity capacitor. The DRWB exploits the differential write scheme, which has been developed originally for the write reduction in SSD, to protect data in the write buffer. Experimental results show that the proposed scheme enables us to achieve the same effect with the NVRAM write buffer, in terms of the data reliability, without noticeable performance degradation.

Abstract: As the reliability of NAND Flash memory keeps degrading, Low-Density Parity-Check (LDPC) codes are widely proposed to extend the endurance of Solid State Drive (SSD). However, implementing powerful decoding algorithm such as soft min-sum algorithm with high decoding speed comes along with higher hardware cost. To achieve efficient hardware cost, we propose a multi-strategy ECC scheme which consists of modified gradient descent bit-flipping (MGDBF), hard min-sum, and soft min-sum decoders. The MGDBF decoder aims to correct most of the erroneous codewords with advantages of high decoding throughput and low hardware cost, while the soft min-sum decoder is targeted to correct codewords with large number of errors under moderate decoding throughput and reasonable hardware cost. In addition, we propose a bi-sectional channel estimation technique which enables on-line estimation of distribution to generate accurate soft information for LDPC decoding with low complexity. The ECC codec and the complete Toggle DDR 1.0 NAND interface control circuits are integrated and fabricated in 90nm CMOS process. The throughput of proposed MGDBF decoder achieves 3.46 Gb/s which satisfies the throughput requirement of both toggle DDR 1.0 and 2.0 NAND interfaces.

Abstract: Disclosed herein are a method and an apparatus for shortening a data comparison test time by using peer-to-peer transfers between peripheral component interconnect express (PCIe) endpoints when testing solid state drive (SSD) devices. A memory device test apparatus performing a data comparison test of a memory device mounted in a downstream port of a peripheral component interconnect express (PCIe) switch by performing a writing process and a reading-back process by a control of a host central processing unit (CPU) includes: a comparison test unit (FPGA) connected to the downstream port of the PCIe switch, performing peer-to-peer communication with the memory device to supply write data to the memory device and receive read-back data from the memory device, and performing the data comparison test.

Abstract: A method is provided to verify that a memory device has been erased and that the device is the originally intended item. Physically uncloneable features of the memory are revealed after erase and form the data for a fingerprint that verifies that the memory has not been exchanged for another memory. A PUF inherent in multiple memory devices included in the memory is revealed upon erase and the PUF is used to create and ID. This ID is compared to the ID for the original unit.

Abstract: The operation of a pool of solid state drives is orchestrated to manage garbage collection and wear leveling. Each individual solid state drive is operated in either an Active Mode in which I/O commands are processed or in a Maintenance Mode in which garbage collection is performed and no I/O commands are processed. The selection of solid state drives in the Active Mode is further selected to achieve wear leveling over the pool of solid state drives. A virtualization layer provides dynamic mapping of virtual volume addresses to physical solid state drives.

Abstract: Methods, systems, and programs are presented for managing a storage device memory. One method includes an operation for receiving a request to pin a volume stored in the storage device. The device includes disk storage and a solid state drive (SSD) cache, where pinned volumes in the storage device have all active volume data in the SSD cache. Further, the method includes an operation for determining the maximum amount of pinnable space in the SSD cache, the maximum amount of pinnable space being calculated based on the sizes of the disk storage and the SSD cache. Further, the method includes operations for determining the available pinning space, which is the maximum amount of pinnable space minus the current amount of pinned data in the SSD cache, and for granting the request to pin the volume when the available pinning space is greater than or equal to a size of the volume.

Abstract: The invention relates to the technical field of electronic equipment storage equipment, in particular to a solid state hybrid drive. The solid state hybrid drive comprises a storage controller and a storage array, wherein the storage array consists of a novel nonvolatile storage chip and a flash memory storage chip. Compared with a traditional NAND or NOR type flash type solid state drive, the solid state hybrid drive is higher in read-write speed and longer in erasing service life. Compared with the solid state drive which adopts a latest technology and is based on the novel nonvolatile storage chip, the solid state hybrid drive is low in cost and high in integration degree and is favorable for saving the power consumption and cost of the solid state drive.

Abstract: The invention relates to the technical field of storage devices, in particular to a solid-state drive and a read-write method thereof. An embedded nonvolatile memory is added to the solid-state drive, data which are randomly read and written most frequently on a flash memory chip in the solid-state drive during the current period are stored in the embedded nonvolatile memory, and due to the fact that the random read-write speed of the embedded nonvolatile memory is high, the random read-write speed of the solid-state drive can be increased to a certain extent, so that the difference between the random read-write speed of the solid-state drive and the random read-write speed of the memory is reduced.

Abstract: Examples may include techniques to recover data from a solid state drive (SSD) using exclusive OR (XOR) parity information Data saved to non-volatile types of block-erasable memory such as NAND memory included in the SSD may be recovered via use of XOR parity information saved to types of write-in-place memory such as a 3-dimensional cross-point memory also included in the SSD

Abstract: With recent advancement on hardware technologies, new general-purpose high-performance devices have been widely adopted, such as the graphics processing unit (GPU) and solid state drive (SSD). GPU may offer an order of higher throughput for applications with massive data parallelism, compared with the multicore CPU. Moreover, new storage device SSD is also capable of offering a much higher I/O throughput and lower latency than a traditional hard disk device (HDD). These new hardware devices can significantly boost the performance of many applications; thus the database community has been actively engaging in adopting them into database systems. However, the performance benefit cannot be easily reaped if the new hardwares are improperly used. In this paper, we propose Hetero-DB, a high-performance database system by exploiting both the characteristics of the database system and the special properties of the new hardware devices in system’s design and implementation. Hetero-DB develops a GPU-aware query execution engine with GPU device memory management and query scheduling mechanism to support concurrent query execution. Furthermore, with the SSD-HDD hybrid storage system, we redesign the storage engine by organizing HDD and SSD into a two-level caching hierarchy in Hetero-DB. To best utilize the hybrid hardware devices, the semantic information that is critical for storage I/O is identified and passed to the storage manager, which has a great potential to improve the efficiency and performance. Hetero-DB aims to maximize the performance benefits of GPU and SSD, and demonstrates the effectiveness for designing next generation database systems.

Abstract: After investigating the data processing characteristics of several scientific applications in various disciplines from bioinformatics to geology, we discover that they share one common feature: raw data is written once onto a storage system and then it is read into memory once for analyzing, after which it will seldom be used in the future. Typically, these scientific applications are running on a cluster where the storage system of each node is composed of an array of hard disk drives (HDDs). Although HDDs are economical, they become increasingly incompetent to meet the high I/O performance requirements imposed by these applications. Flash memory based solid-state-drives (SSDs), on the other hand, can provide a high performance and energy-efficiency. Still, they are relatively expensive than HDDs. In this paper, we propose a cost-effective yet high-performance storage architecture called SOHO (SSD-Workshop-HDD-Warehouse) for these write-once-read-once scientific applications like seismic wave analysis. Its basic idea is to process raw data in the workshop (i.e., SSD), and then, the processed data is moved to the warehouse (i.e., HDD) later. Experiments using both real-world scientific applications and synthetic traces demonstrate that on average SOHO outperforms a pure HDD storage system in mean response time by 78.25%. Compared to a pure SSD system, it only degrades mean response time by less than 3.11%.