Abstract: An improved programmable logic cell (1) for use in a programmable logic array comprising cells which are arranged in two-dimensional matrix of rows and columns and are interconnected by a two-dimensional array of direct connections between a cell (1) and its four nearest neighbors, one to its left (or to the West) (3a, 3b, 7a, 7b) and one to its right (or to the East) (5a, 5b, 9a, 9b), one above it (or to the North) (2a, 2b, 6a, 6b) and one below it (or to the South) (4a, 4b, 8a, 8b). Each cell receives input (s) from each of its nearest neighbors and additional input(s) from a bus, pin, or neighbor and may be programmed to generate a variety of logical functions at its outputs which connect to the cell's four nearest neighbors. The core of the improved logic cell (fig.2) comprises two upstream gates (21, 23) the outputs of which feed two downstream gates (28, 41), one of which is an exclusive-OR gate (28) which feeds a downstream register (33). Additional programmable connections and other logic augment the cell core to produce cell embodiments which can be configured to efficiently implement various logical functions. Among the functions which may be implemented by the improved cell are a number of two-level combinational functions (such as multiplexing) and sequential functions (such as counting and shifting). A variety of cell embodiments based on the improved cell core are illustrated.

Abstract: A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit.

Abstract: A technique is described for testing the performance of a target electronic system ultimately employing an ASIC comprising a core cell and surrounding logic, using an inchoate (designed, but not yet fabricated) ASIC on an interim basis. In one embodiment, a Q-part, or qualification part, which is essentially a bond-out of the core cell, is used in conjunction with programmable logic devices configured to perform the function of the surrounding logic. The Q-part and programmable logic are interconnected on a pod, and plugged into an interim version of a target electronic system. In another embodiment, the Q-part is software-simulated and interconnected on the pod to programmable logic devices. The programmable logic devices may be programmed either on-pod or off-pod, and signals incident to the operation of the pod plugged into the interim electronic system can be monitored and controlled.

Abstract: The logic cell of the current invention is useful in a field programmable logic device, particularly a device in which an interconnect structure is interconnected by antifuses, and logic cells are programmed using pass transistors. All input leads of the logic cell can be selectively inverted. The output signal from one logic cell can be cascaded as input to the adjacent cell for efficiently computing wide functions. An optional feedback path allows the cell to be optionally used for sequential functions without the delay caused by a feedback path through field programmed connections. Configuration units can serve the multiple purposes of selectively applying programming voltages to the interconnect structure, shifting in configuration information for configuring the interconnect structure, and capturing and shifting out states of the interconnect lines. A novel output buffer allows 3-state control from multiple sources. A novel reset circuit allows only the cells used as sequential elements to be reset, and only when reset would not cause contention with an input data signal.

Abstract: A user-programmable interconnect architecture, which may be used for logic arrays for digital and analog system design, is disclosed. In one embodiment, a plurality of logic cells or modules in a matrix are connected by vertical and horizontal wiring channels. The wiring channels may in turn be programmed by the user to interconnect the various logic cells to implement the required logic function. The wiring channels comprise wiring segments connected by normally open programmable elements situated at the intersection of any two segments to be connected.

Abstract: This authors explore the effect of logic block architecture on the speed of a field-programmable gate array (FPGA). Four classes of logic block architecture are investigated: NAND gates, multiplexer configurations, lookup tables, and wide-input AND-OR gates. An experimental approach is taken, in which each of a set of benchmark logic circuits is synthesized into FPGAs that use different logic blocks. The speed of the resulting FPGA implementations using each logic block is measured. While the results depend on the delay of the programmable routing, experiments indicate that five- and six-input lookup tables and certain multiplexer configurations produce the lowest total delay over realistic values of routing delay. The fine grain blocks, such as the two-input NAND gate, exhibit poor performance because these gates require many levels of logic block to implement the circuits and hence require a large routing delay. >

Abstract: A structure and method for in-system programming of a programmable logic device are provided. The in-system programming structure provides one dedicated pin for in-system programming function, additional in-system programming pins are multiplexed with programmable input/output pins used in functional operations. When an enable signal is received at the dedicated pin, the multiplexed pins relinquish their roles as programmable input/output pin to become in-system programming pins. A state machine controls the programming steps. The in-system programming structure can be cascaded in a "daisy chain" fashion.

Abstract: An approach to the decomposition of incompletely specified Boolean functions is introduced, and its application to lookup-table-based field programmable gate array (FPGA) mapping is described. Three methods are developed: fast graph coloring to perform a quasi-optimum 'don't care' assignment; variable partitioning to quickly find the 'best' partitions; and local transformation to transform a nondecomposable function into several decomposable ones. The methods perform global optimization of the input function. A short description of a FPGA mapping program (TRADE) and an evaluation of its results are provided. >

Abstract: AnyBoard, a low-cost, field programmable gate array (FPGA)-based, reconfigurable rapid-prototyping system is described. The system hardware organization and software tools that help users automatically map designs to the FPGAs and manage the design process are discussed. The implementation of a pattern generator design is presented to illustrate the system's effectiveness. >

Abstract: A programmable chip enable provides for enabling or disabling an integrated circuit in response to a selected one of a plurality of logic signals. In a specific application, the programmable enable function is used in combination with a plurality of field programmable memory devices. The enable functions of the respective devices are programmed to prevent simultaneous enablement of the memory devices which have their outputs connected together.

Abstract: The present invention is directed to a programmable logic circuit used as an arbiter to control access to a shared resource, eg a system bus, by N devices in a computer system The programmable arbiter according to the present invention, implements a logic design with sufficient flexibility to accommodate and selectively incorporate features of several different arbitration schemes including a straight priority scheme, a programmable arbitration, and a rotating priority arbitration scheme In addition to these arbitration schemes, the arbiter of the present invention supports an extended programmable arbitration scheme whereby a device which is requesting access to the shared resource may be granted access to the resource even if it has used up its allocated share of bandwidth if there are no other devices requesting access to the shared resource Furthermore, bus bandwidth may be allocated to particular device or to a group of devices at a particular priority level In addition to providing for programmable allocation of bus bandwidth, the arbiter of the present invention permits the number of clock cycles allocated per bus window for one requesting device to be different from the number of clock cycles allocated per bus window for another device In this manner, the size of the bus window can be designed to accommodate the individual requirements of each device permitting maximization of both the device's and the system's overall efficiency

Abstract: A logic system comprising one or more logic networks that can perform a variety of preconfigured or preconfiguarable logic functions. Each logic network is functionally separate from but operatively associated with one or more programmable circuits from which the logic network receives various logic signals. A first logic signal selects or preconfigures the desired logic function to be performed by the or each logic network while a second logic signal controls the operation of the selected logical function. The first logic signal can select a particular logic function to be performed by the logic network based on the contents of programmable cells in the network that are separate from the programmable circuits that supply the logic signals. Alternatively, the first logic signals can switch between various sub-networks each dedicated to performance of a preconfigured logic function. In this manner, the programmable circuit can essentially be dedicated to selecting which of various predetermined logic functions is to be utilized and is relieved of significant functional overhead associated with data manipulation. This can permit a smaller size programmable logic, gate or memory array to be used to control a logic operation of a given complexity, or a given size of array to control more complex operations. Both the programmable circuit(s) and the logic network(s) can be integrated in a single semiconductor chip.

Abstract: A programmable logic device comprises a semiconductor with configurable circuitry, an input circuit for encrypted data to determine the configuration of the circuitry, decrypting circuitry responsive to a key value held in a non-volatile data store, and volatile storage circuitry for holding decrypted configuration data. Encrypting circuitry uses the same key value to encrypt configuration data and stores the encrypted configuration data for use in the programmable logic device.

Abstract: A programmable logic device (PLD) with an output macrocell circuit is disclosed. Specifically, there is a field programmable logic array (FPLA) using a dedicated product term for macrocell control. Particularly, the macrocells contain a faster, more flexible, and exclusive feedback line as well as an exclusive external-input line from an input/output (I/O) pad for a registered mode of operation. Moreover, there is a registered mode macrocell which has 1) a feedback path for the registered mode signals which is activated even when the I/O pad driver is disabled, 2) an input path, to the logic circuitry, over an I/O pad, 3) a feedback path for the registered mode signals while outputting the same registered mode signals, and 4) a feedback path which avoids the unnecessary signal noise emanating from the use of a 3-state device or output driver. In addition, the macrocell allows for a disabled tri-state and still have the feedback intact for the combinatorial mode; thus, avoiding the extra noise that a tri-state creates.

Abstract: A programmable logic device (PLD) cell is used to construct a high density high performance programmable logic device (PLD). The PLD cell includes two programmable logic block cells. The PLD cell also includes an I/O cell and an input macrocell. In addition the PLD cell includes a sub-bank of a programmable output switch matrix bank and a sub-bank of a programmable input switch matrix bank. Each programmable logic block cell includes a multiplicity of product terms. At least one product term in the cluster is programmably available to the cluster. When the product term is disconnected from the cluster, the product term is used for control of the polarity of the logic macrocell output signal or asynchronous functions. Thus, the programmably connectable product term can be used for either synchronous or asynchronous operations. If the programmably connectable and disconnectable product term is connected to the product term cluster, the programmable logic block cell is used for synchronous operations. However, since each product term cluster is associated with a logic macrocell, the logic macrocell can be individually configured for asynchronous operation by simply disconnecting the apropriate produce term from the product term cluster and using the product term for the desired asynchronous function. Thus, a single PLD built using the programmable logic block cells supports simultaneously synchronous and asynchronous operations.

Abstract: A routing-driven technology mapper for lookup-table, (LUT)-based field-programmable gate arrays (FPGAs) is presented. The approach is based on performing mapping aimed at routing feasibility. For an FPGA of given size (number of LUTs), the logic being implemented is distributed in such a manner that the total wire length is minimized and the routing resources are not overutilized. Simulated annealing is used to perform mapping, placement, and global routing in tandem. The algorithm can handle both combinational and sequential logic circuits, and has been implemented for combinational circuits. Experiments on MCNC benchmark circuits show encouraging results. >

Abstract: The logic cell of the current invention is useful in a field programmable logic device, particularly a device in which an interconnect structure is interconnected by antifuses, and logic cells are programmed using pass transistors. All input leads of the logic cell can be selectively inverted. The output signal from one logic cell can be cascaded as input to the adjacent cell for efficiently computing wide functions. An optional feedback path allows the cell to be optionally used for sequential functions without the delay caused by a feedback path through field programmed connections. Configuration units can serve the multiple purposes of selectively applying programming voltages to the interconnect structure, shifting in configuration information for configuring the interconnect structure, and capturing and shifting out states of the interconnect lines. A novel output buffer allows 3-state control from multiple sources. A novel reset circuit allows only the cells used as sequential elements to be reset, and only when reset would not cause contention with an input data signal.

Abstract: Field programmable gate arrays (FPGA) use interconnect devices to link logic blocks ranging from single transistors to macrocells. Interconnect devices in use today include MOSFET (SRAM), floating gate memory devices, dielectric and amorphous silicon antifuses. Comparative characteristics of the interconnect devices are discussed. >

Abstract: A programmable logic array comprising cells and a bus network in which the cells are arranged in a two-dimensional matrix of rows and columns and are interconnected by the bus network. The cells are also interconnected by a two-dimensional array of direct connections between a cell and its four nearest neighbors, one to its left (or to the West), one to its right (or to the East), one above it (or to the North) and one below it (or to the South). Each cell comprises eight inputs, eight outputs, means for multiplexing the eight inputs onto two leads and logic means that operate in response to the signals on the two leads to produce output signals which are applied to the eight outputs. The bus network comprises a local, a turning and an express bus for each row and column of the array and repeater means for partitioning said buses of a given row or column so as to form bus segments. The bus network provides for transfer of data to the cells of the array without using the cells as individual wires.

Abstract: The authors address the problem of synthesis for a popular class of programmable gate array architectures, the multiplexer-based architectures. They present improved techniques for minimizing the number of basic blocks used to implement a combinational circuit. One source of improvement is the use of if-then-else DAGs (directed acyclic graphs) as subject graphs along with BDDs (binary decision diagrams). An important contribution is a very fast algorithm which always gives a match for a function onto the basic block of the architecture, when one exists. Results obtained on a number of benchmark examples are given. >

Abstract: The present invention is used in an FPGA device having programmable logic cells and a programmable interconnect array. In a preferred embodiment in which the logic cells are programmed using transistors controlled by memory cells and the interconnect structure is programmed using antifuses, a configuration control unit (CCU) of the present invention can accomplish three functions: 1) applying programming voltages to terminals of the interconnect antifuses; 2) configuring the logic cells; and 3) reading status of signals on the interconnect structure. The CCUs are connected together into a shift register. Each CCU connects to a horizontal or vertical interconnect line. At intersections of these interconnect lines are antifuses. By loading logical 1's into the two CCUs, it is possible to address the antifuse at the intersection of the two interconnect lines. A voltage difference can then be directed to the two terminals of that antifuse for programming the antifuse. After antifuses are programmed, configuration information is shifted into the CCUs to configure the logic cells. These same CCUs can be used to capture the logical states of each of the interconnect lines, each CCU capturing one signal present on an interconnect line to which that CCU connects. The captured data can then be shifted out through the shift register.

Abstract: In this paper, we consider the problem of generating small (compact) test sets for single transition and CMOS stuck-open faults in combinational logic circuits. In addition, we propose that to generate test sets that cover a wide range of physical defects, a test set to detect faults of different models should be derived. Specifically, we address the problem of generating small and comprehensive test sets by considering the CMOS stuck-open and the single transition fault models together. We propose a dynamic test compaction technique for two-pattern tests, which exploits the test compaction strategies developed for stuck-at faults, and performs dynamic test vector overlap to derive small test sets. We present experimental results for ISCAS-85 combinational circuits and fully scanned versions of ISCAS-89 sequential circuits to illustrate the efficacy of the proposed test compaction technique.

Abstract: The present invention provides a dedicated memory circuit which supports the generation of parity data in connection with the storing of data. This improved memory circuit allows the parity generation to be done remotely from the CPU while consuming less time. The memory array is provided with its data output being connected to combinational logic. Another input to combinational logic is for external data. The data already in the array and the new data are combined to the combinational logic, preferably an exclusive-or arrangement, to produce the parity data which is then returned to the memory array. A latch is provided between the exclusive-or logic and the memory array data lines to allow isolation of the data during the two cycles of the read out of the array and the right back to the array after the exclusive-or.

Abstract: A programmable logic device (PLD) is disclosed which can efficiently, in a real estate sense, emulate a Mealy state machine. Specifically, there is a PLD which has: (1) a programmable logical AND and two programmable logical OR arrays, similar to a field programmable logic array; and (2) one of the two fully programmable OR array generates a next state of the circuit and the second OR array generates an output responsive to both the inputs and the current state.

Abstract: The authors present a new approach to technology mapping for area and delay for truth-table-based field programmable gate arrays. They view the area and delay optimizations during technology mapping as a case of clique partitioning for which an efficient heuristic was developed. Alternate decompositions were explored by using Shannon expansion. Experimental results are included that were obtained by this approach for area and delay optimization on a number of benchmark examples. >

Abstract: A semiconductor integrated circuit capable of electrically writing functions according to this invention comprises a plurality of logical blocks capable of electrically writing functions and wire elements capable of programmably connecting the logical blocks to each other. Each of the logical blocks includes a gate element as an output buffer having a control terminal. The gate element assumes a high impedance state when inputting a control signal to the control terminal. An output of the logical block is thereby made unable; or the respective logical blocks are directly wired-connectable to effect logical sum outputting. Alternatively, the gate element assumes two output states of an open drain output and a totem-pole output. Hence, in the semiconductor integrated circuit of this invention, it is possible to improve a gate using efficiency of the small-sized programmable logical blocks and attain a high-density and high-integrated programmable logic device.

Abstract: In a programmable logic device having a plurality of gates capable of being programmed according to a plurality of product terms representing logic functions, an apparatus for allocating the product terms to a plurality of outputs. A first set of product terms are steerable to one of at least two outputs. A second set of product terms is permanently assigned to a predetermined output. The second set is comprised of more product terms than the first set, wherein the average number of product terms per output is low, yet a user has the flexibility of implementing logic functions requiring a relatively large number of product terms.

Abstract: An output logic macrocell ('OLMC' 30a) containing an exclusive OR gate (309a) is associated with the product terms (P) and other outputs of a logic block such as a programmable logic array. The OLMC (30a) is capable of providing enhanced functions, including cascaded exclusive OR gates, function sharing, T and J-K flip-flop emulation, asynchronous clocking, and reset selection. In addition, a logic block is used as the source of an asynchronous clock pulse and is connected to the global clock distribution system (320a) of a device such as a high density programmable logic device.