Abstract: A laminated structure comprises a first layer comprising a crystal with six-fold symmetry, and a second layer comprising a metal oxynitride crystal formed on the first layer, wherein the second layer comprises at least one element selected from the group consisting of In, Ga, Si, Ge and Al, N, O and Zn, as main elements, and wherein the second layer has in-plane orientation.

Abstract: A small diameter flexible electrode designed for subcutaneous in vivo amperometric monitoring of glucose is described. The electrode is designed to allow “one-point” in vivo calibration, i.e., to have zero output current at zero glucose concentration, even in the presence of other electroreactive species of serum or blood. The electrode is preferably three or four-layered, with the layers serially deposited within a recess upon the tip of a polyamide insulated gold wire. A first glucose concentration-to-current transducing layer is overcoated with an electrically insulating and glucose flux limiting layer (second layer) on which, optionally, an immobilized interference-eliminating horseradish peroxidase based film is deposited (third layer). An outer (fourth) layer is biocompatible.

Abstract: We show that the optical constants of graphene in the visible range can be estimated by means of a very simple procedure involving their consistence with universal optical conductivity and experimentally measured optical spectra, within the framework of Fresnel coefficients calculation. The obtained complex refractive index allows for accurate prediction of the optical behavior of graphene in the visible range, from the two-dimensional limit (single atomically thick graphene layer) to the bulk limit (graphite). Therefore, it may result very useful for quantitative optical analysis of graphene layers and graphitic structures in general.

Abstract: Provided is a light emitting diode (LED) manufactured by using a wafer bonding method and a method of manufacturing a LED by using a wafer bonding method. The wafer bonding method may include interposing a stress relaxation layer (33) formed of a metal between a semiconductor layer (20) and a bonding substrate (31). When the stress relaxation layer is used, stress between the bonding substrate and a growth substrate may be offset due to the flexibility of metal, and accordingly, bending or warpage of the bonding substrate may be reduced or prevented.

Abstract: We report on large energy pulse generation in an erbium-doped fiber laser passively mode-locked with atomic layer graphene. Stable mode locked pulses with single pulse energy up to 7.3 nJ and pulse width of 415 fs have been directly generated from the laser. Our results show that atomic layer graphene could be a promising saturable absorber for large energy mode locking.

Abstract: A tissue electrode assembly includes a membrane configured to form an expandable, conformable body that is deployable in a patient. The assembly further includes a flexible circuit positioned on a surface of the membrane and comprising at least one base substrate layer, at least one insulating layer and at least one planar conducting layer. An electrically-conductive electrode covers at least a portion of the flexible circuit and a portion of the surface of the membrane not covered by the flexible circuit, wherein the electrically-conductive electrode is foldable upon itself with the membrane to a delivery conformation having a diameter suitable for minimally-invasive delivery of the assembly to the patient.

Abstract: We utilize an organic polymer buffer layer between graphene and conventional gate dielectrics in top-gated graphene transistors. Unlike other insulators, this dielectric stack does not significantly degrade carrier mobility, allowing for high field-effect mobilities to be retained in top-gate operation. This is demonstrated in both two-point and four-point analysis and in the high-frequency operation of a graphene transistor. Temperature dependence of the carrier mobility suggests that phonons are the dominant scatterers in these devices.

Abstract: The fabrication of many devices in modern technology requires techniques for growing thin films. As devices miniaturize, manufacturers will need to control thin film growth at the atomic level. Because many devices have challenging morphologies, thin films must be able to coat conformally on structures with high aspect ratios. Techniques based on atomic layer deposition (ALD), a special type of chemical vapor deposition, allow for the growth of ultra-thin and conformal films of inorganic materials using sequential, self-limiting reactions. Molecular layer deposition (MLD) methods extend this strategy to include organic and hybrid organic−inorganic polymeric materials. In this Account, we provide an overview of the surface chemistry for the MLD of organic and hybrid organic−inorganic polymers and examine a variety of surface chemistry strategies for growing polymer thin films. Previously, surface chemistry for the MLD of organic polymers such as polyamides and polyimides has used two-step AB reaction cycle...

Abstract: To improve bonding strength and improve reliability of an SOI substrate in bonding a semiconductor substrate and a base substrate to each other even when an insulating film containing nitrogen is used as a bonding layer, an oxide film is provided on the semiconductor substrate side, a nitrogen-containing layer is provided on the base substrate side, and the oxide film formed on the semiconductor substrate and the nitrogen-containing layer formed over the base substrate are bonded to each other. Further, plasma treatment is performed on at least one of the oxide film and the nitrogen-containing layer before bonding the oxide film formed on the semiconductor substrate and the nitrogen-containing layer formed over the base substrate to each other. Plasma treatment can be performed in a state in which a bias voltage is applied.

Abstract: We utilize an organic polymer buffer layer between graphene and conventional gate dielectrics in top-gated graphene transistors. Unlike other insulators, this dielectric stack does not significantly degrade carrier mobility, allowing for high field-effect mobilities to be retained in top-gate operation. This is demonstrated in both two-point and four-point analysis, and in the high-frequency operation of a graphene transistor. Temperature dependence of the carrier mobility suggests that phonons are the dominant scatterers in these devices.

Abstract: We demonstrate an effective method for depositing smooth silver (Ag) films on SiO2/Si(100) substrates using a thin seed layer of evaporated germanium (Ge). The deposited Ag films exhibit smaller root-mean-square surface roughness, narrower peak-to-valley surface topological height distribution, smaller grain-size distribution, and smaller sheet resistance in comparison to those of Ag films directly deposited on SiO2/Si(100) substrates. Optically thin (∼10−20 nm) Ag films deposited with ∼1−2 nm Ge nucleation layers show more than an order of magnitude improvement in the surface roughness. The presence of the thin layer of Ge changes the growth kinetics (nucleation and evolution) of the electron-beam-evaporated Ag, leading to Ag films with smooth surface morphology and high electrical conductivity. The demonstrated Ag thin films are very promising for large-scale applications as molecular anchors, optical metamaterials, plasmonic devices, and several areas of nanophotonics.

Abstract: Optical emission spectroscopy, fast video imaging and coating characterization are employed to investigate AC plasma electrolytic oxidation (PEO) of magnesium alloys The findings revealed initiation and gradual increase in the number of discharges after 2–4 ms of each anodic pulse once a critical voltage was reached No discharges were observed during the cathodic half-cycles The lifetimes of discharges were in the range of 005–4 ms A transition in the voltage-time response, accompanied by a change in the acoustic and optical emission characteristics of discharges, was associated with the development of an intermediate coating layer with an average hardness of 270–450 HV 005 The coatings grew at a rate in the range 40–75 µm min − 1 , depending on the substrate composition Regardless of the substrate, the coatings consisted of MgO and Mg 2 SiO 4 , with incorporation of alloying element species Electrolyte species were mainly present in a more porous layer at the coating surface, constituting 20–40% of the coating thickness A thin barrier layer consisting of polycrystalline MgO was located next to the alloy The corrosion rate of the magnesium alloys determined using potentiodynamic polarization in 35 wt% NaCl was reduced by 2–4 orders of magnitude by the PEO treatment

Abstract: We present a robust and cost-effective coating method to fabricate long-term durable superhydrophobic and—simultaneously—antireflective surfaces by a double-layer coating comprising trimethylsiloxane (TMS) surface-functionalized silica nanoparticles partially embedded into an organosilica binder matrix produced through a sol−gel process A dense and homogeneous organosilica gel layer was first coated onto a glass substrate, and then, a trimethylsilanized nanospheres-based superhydrophobic layer was deposited onto it After thermal curing, the two layers turned into a monolithic film, and the hydrophobic nanoparticles were permanently fixed to the glass substrate Such treated surfaces showed a tremendous water repellency (contact angle = 168°) and stable self-cleaning effect during 2000 h of outdoor exposure Besides this, nanotextured topology generated by the self-assembled nanoparticles-based top layer produced a fair antireflection effect consisting of more than a 3% increase in optical transmittance

Abstract: Tungsten oxide (WO3) was inserted as an anode interfacial layer between the photoactive layer and top electrode in inverted polymer solar cells (PSCs) with nanocrystalline titanium dioxide as an electron selective layer. The device with WO3 exhibited a remarkable improvement in power conversion efficiency compared with that without WO3, which indicated that WO3 efficiently prevented the recombination of charge carriers at the organic/top electrode interface. The dependence of the device performances on WO3 film thickness and different top metal electrodes was investigated. Transparent inverted PSCs with thermally evaporable Ag/WO3 as a transparent anode were also investigated when introducing a WO3 buffer layer.

Abstract: We report graphene films composed mostly of one or two layers of graphene grown by controlled carbon precipitation on the surface of polycrystalline Ni thin films during atmospheric chemical vapor deposition(CVD). Controlling both the methane concentration during CVD and the substrate cooling rate during graphene growth can significantly improve the thickness uniformity. As a result, one- or two- layer graphene regions occupy up to 87% of the film area. Single layer coverage accounts for 5-11% of the overall film. These regions expand across multiple grain boundaries of the underlying polycrystalline Ni film. The number density of sites with multilayer graphene/graphite (>2 layers) is reduced as the cooling rate decreases. These films can also be transferred to other substrates and their sizes are only limited by the sizes of the Ni film and the CVD chamber. Here, we demonstrate the formation of films as large as 1 in2. These findings represent an important step towards the fabrication of large-scale high-quality graphene samples.

Abstract: A thin film transistor (TFT) using an oxide semiconductor as an active layer, a method of manufacturing the TFT, and a flat panel display device having the TFT include source and drain electrodes formed on a substrate; an active layer formed of an oxide semiconductor disposed on the source and drain electrodes; a gate electrode; and an interfacial stability layer formed on at least one of top and bottom surfaces of the active layer. In the TFT, the interfacial stability layer is formed of an oxide having a band gap of 3.0 to 8.0 eV. Since the interfacial stability layer has the same characteristics as a gate insulating layer and a passivation layer, chemically high interface stability is maintained. Since the interfacial stability layer has a band gap equal to or greater than that of the active layer, charge trapping is physically prevented.

Abstract: High density through silicon via (TSV) is a key in fabricating three-dimensional (3-D) large-scale integration (LSI). We have developed polycrystalline silicon (poly-Si) TSV technology and tungsten (W)/poly-Si TSV technology for 3-D integration. In the poly-Si TSV formation, low-pressure chemical vapor deposition poly-Si heavily doped with phosphorus was conformally deposited into the narrow and deep trench formed in a Si substrate after the surface of Si trench was thermally oxidized. In the W/poly-Si TSV formation, tungsten was deposited into the Si trench by atomic layer deposition method after the poly-Si deposition, where poly-Si was used as a liner layer for W deposition. The 3-D microprocessor test chip, 3-D memory test chip, 3-D image sensor chip, and 3-D artificial retina chip were successfully fabricated by using poly-Si TSV.

Abstract: Provided is a thin film transistor capable of improving reliability in the thin film transistor including an oxide semiconductor layer. A thin film transistor including: a gate electrode; a gate insulating film formed on the gate electrode; an oxide semiconductor layer forming a channel region corresponding to the gate electrode on the gate insulating film; a channel protective film formed at least in a region corresponding to the channel region on the oxide semiconductor layer; and a source/drain electrode. A top face and a side face of the oxide semiconductor layer are covered with the source/drain electrode and the channel protective layer on the gate insulating film.

Abstract: A capacitive touch panel includes a substrate having a pattern-forming surface, a color pixel layer formed on the substrate, and a patterned conductive layer formed on the pattern-forming surface of the substrate. The patterned conductive layer includes a plurality of first electrode units, a plurality of second electrode units, a plurality of spaced apart first conductive lines, and a plurality of spaced apart second conductive lines. The first electrode units are capacitively coupled to the second electrode units so as to form a plurality of two dimensionally arranged capacitive sensing units. Each of the first electrode units includes a plurality of first electrodes. Each of the first conductive lines is connected to and extends along the pattern-forming surface from at least one of the first electrodes of a respective one of the first electrode units into a bonding area of the pattern-forming surface. The second conductive lines extend respectively from the second electrode units into the bonding area, and do not cross the first conductive lines.

Abstract: A method for etching features in a dielectric layer through a photoresist (PR) mask is provided. The PR mask is patterned using laser light having a wavelength not more than 193 nm. The PR mask is pre-treated with a noble gas plasma, and then a plurality of cycles of a plasma process is provided. Each cycle includes a deposition phase that deposits a deposition layer over the PR mask, the deposition layer covering a top and sidewalls of mask features of the PR mask, and a shaping phase that shapes the deposition layer deposited over the PR mask.

Abstract: The present invention provides a substrate processing method to process a substrate including at least a process layer, an intermediate layer, and a mask layer are stacked in this order. The mask layer includes an aperture configured to expose a portion of the intermediate layer. The substrate processing method includes a material deposition step of depositing a material on a side surface of the aperture and exposing a portion of the process layer by etching the exposed portion of the intermediate layer by plasma generated from a deposit gas, and an etching step of etching the exposed portion of the process layer.

Abstract: High density through silicon via (TSV) is a key in fabricating three-dimensional (3-D) large-scale integration (LSI). We have developed polycrystalline silicon (poly-Si) TSV technology and tungsten (W)/poly-Si TSV technology for 3-D integration. In the poly-Si TSV formation, low-pressure chem- ical vapor deposition poly-Si heavily doped with phosphorus was conformally deposited into the narrow and deep trench formed in a Si substrate after the surface of Si trench was thermally oxidized. In the W/poly-Si TSV formation, tungsten was deposited into the Si trench by atomic layer deposition method after the poly-Si deposition, where poly-Si was used as a liner layer for W deposition. The 3-D microprocessor test chip, 3-D memory test chip, 3-D image sensor chip, and 3-D artificial retina chip were successfully fabricated by using poly-Si TSV.

Abstract: PROBLEM TO BE SOLVED: To provide an organic electroluminescent device easy to manufacture and excellent in durability. SOLUTION: In the organic electroluminescent device having at least a polymer light-emitting layer between a pair of an anode and a cathode with at least either transparent or translucent, a cathode surface of an opposite side from a side with a polymer light-emitting layer arranged, has an oxygen permeability rate below 200(cm 3 /m 2 24h atm) and a moisture vapor permeability rate below 200 (g/m 2 24h atm), and is covered by a base material made of a glass or a gas barrier polymer. An adhesive layer is provided on the cathode surface of the opposite side from the side with a polymer light-emitting layer arranged, a base material made of the glass or the gas barrier polymer is adhered on the adhesive layer, so that they are adhered together. COPYRIGHT: (C)2008,JPO&INPIT