Abstract: Structures and techniques are provided for allowing one or more of the following actions to occur within a Complex Programmable Logic Device (CPLD): (1) Elective use of a fast, allocator-bypassing path (e.g., a fast 5-PT path) in combination with in-block simple or super-allocation; (2) Elective use of an OSM-bypassing path for signals that do not need pin-consistency; (3) Automatic re-routing of output enable signals that corresponding to output signals which are re-routed for pin-consistency purposes; (4) Global distribution of globally-usable output enable signals; (5) Elective use of two-stage steering to develop complex sum-of-clusters terms where fast path or simple allocation will not be sufficient; and (6) Use of unidirectional super-allocation with stage- 2 wrap-around in designs having about 24 or less macrocell units per logic block. Techniques are provided for concentrating the development of complex function signals (e.g., ≧80 PT's) within singular logic blocks so that the development of such complex function signals does not consume inter-block interconnect resources. One CPLD configuring method includes the machine-implemented steps-of first identifying middle-complexity functions that are achievable by combined simple or super-allocation based development in one logic block and fast-path completion in the same or a second logic block; and configuring the CPLD to realize one or more of the functions identified in the first identification step by simple or super-allocation based development in one logic block and fast-path completion in the same or a second logic block.

Abstract: Programmable Logic Controllers ensure the control of many reactive systems. These controllers are most of the time programmed with the languages defined in the IEC 61131-3 standard. Our goal is the verification of safety properties of programs written in one of these languages: the Ladder Diagram. The main approaches in this field are based on Model-Checking. We propose in this article a Theorem-Proving method by defining a formal framework to express and handle the Ladder Diagram programs with a specific algebra. Firstly, we translate the specific statements of the language into this algebra and we give some general theorems. Then, we present on an example an analysis leading to the verification of safety properties.

Abstract: A programming method efficiently programs programmable logic devices of the type having specialized multiplier blocks that include multipliers and other arithmetic function elements Such blocks can be used to perform certain multiplication and multiplication-related functions more efficiently than general-purpose programmable logic In order to efficiently program devices having such specialized multiplier blocks, so that they are used to their full potential and so that the maximum number of multiplier-related functions can be accommodated on a single programmable logic device, the programming method pre-processes the netlist of function blocks in a user's programmable logic design, grouping multiplication and multiplication-related functions efficiently The method takes into account limitations imposed by the structure of the specialized multiplier blocks, in addition to location constraints imposed by the user and location constraints dictated by the need for certain functions be carried out near where certain other functions are carried out

Abstract: Methods and systems are disclosed for automatically generating an execution order for a control system function block diagram. The input data availability is determined for the inputs of the function blocks in the diagram, and an execution order is generated for the function block diagram according to the input data availability for the function block inputs. Also disclosed are methods and systems for generating a control routine from a function block diagram having a plurality of function blocks, wherein the control routine is generated from the function block diagram according to the execution order.

Abstract: In this paper we present an algorithm to convert a controller automaton synthesized by the Ramadge-Wonham (RW) method to a ladder logic diagram. The subject of conversion from RW controller to ladder logic is not new and has already been addressed by many researchers. Our method takes a new look at this subject. We not only make sure that the same sequences of events can be generated by both the RW controller and its converted ladder logic (as done by other related literature), but we also guarantee the implementation of the converted ladder logic as a PLC program. Specifically, we use the IDEF3 standard, which views a manufacturing system as a set of activities and their required resources. We consider the resource events to define the forcing mechanisms of ladder logic, as the original RW controller cannot model these mechanisms. We also use external signals to resolve the inherent conflicts of RW controller that cannot be tolerated under a forcing controller such as ladder logic. Two examples are presented to illustrate the applicability of the proposed algorithm.

Abstract: An interface or display routine is provided for use in viewing and configuring a function block that performs integrated optimization and control within a process control system. The interface routine may enable a user to view or configure variables, values or other parameters associated with the integrated optimization and control block within the process control system. For example, the interface routine may display the current operating state of the integrated function block, may enable a user to select inputs and output of the function block for use in providing integrated optimization and control, may enable a user to select a particular or desired optimization function for use in the function block, etc. The interface routine may also display the multiple input output curves associated with the optimizer and the controller sections of the integrated function block in a manner that provides ease of view and selection of these curves as part of the algorithm used by the integrated function block.

Abstract: MAX 7000 series are the high integrate multiple programmable logic in the industry, which is fast input setup and provides several system clock and programmable speed power optimization. The MAX 7000 additional out put can be controlled, can restore the program in the best way and unable to be erased up easily.

Abstract: Method and apparatus for testing a device embedded in a programmable logic device is described. Because an embedded device, such as a microprocessor core, comprises more input and output pins than a programmable logic device, such as a field programmable gate array, in which it is located, providing a test vector wider than the number of external input and output pins of the programmable logic device is problematic. To solve this problem, at least a portion of the programmable logic device is programmed to function as a vector controller, where a test vector may be provided to the vector controller in sections, reassembled by the vector controller and provided to the embedded device after reassembly. Moreover, a test vector result in response to the test vector input is obtained by the vector controller and sectioned for outputting.

Abstract: A reconfigurable programmable logic system including a programmable logic device and an associated processor is configured using a configuration file including (a) instructions for configuring the programmable logic device as one or more peripherals to be used by the processor, and (b) a list of the peripherals to be configured in the programmable logic. The processor uses the peripheral data from the configuration file to load the appropriate drivers, create all necessary instances of the drivers and optionally to pass parameters for any necessary initial command after each driver is loaded. Optionally, each time the system is configured, any previously loaded drivers are first unloaded.

Abstract: The paper presents the considerations relating to the methods of analysis of a ladder diagram created for a small programmable controller (PLC) of compact type which is equipped with a simple keyboard for entry of such a diagram. Because of the fact that the compact PLC was built using a standard microcontroller with small calculation power the authors met difficulties with the translation of the control program to the binary code. It was necessary to make a decision that a ladder diagram would be not compiled but interpreted during program execution. The method of column by column analysis of the ladder diagram was chosen as the most effective. The particular application of this method for a small compact PLC is presented in detail in the paper.

Abstract: The states of a logic circuit block are set as operation start states and operation end states. An instruction to be analyzed is selected from input/output instruction information. An input signal corresponding to the selected instruction is applied to an RT (Register Transfer)-level model that is in the operation start state. Then, the input signal value applied to the RT-level model is changed. In order to extract operation of the logic circuit block, the RT-level model is analyzed until it reaches the operation end state. An operation model of the logic circuit block is produced based on the extracted operations. In this way, the model of the logic circuit block specifically described at RT level can be converted into a high abstraction-level model including no concept of time.

Abstract: A controller comprising a pipeline including a plurality of connected sequential elements wherein a first sequential element is connected to one or more transaction sources; a flow control logic including at least one resource utilization value register; resource allocation logic responsive to a transaction valid signal and one or more adjustment inputs, and comparison logic having a threshold value and a transaction control signal output connected to the one or more transaction sources; pipeline control logic having an adjustment output connected to the resource allocation logic; and a resource control logic having an output connected to an adjustment input of the resource allocation logic.

Abstract: A field programmable gate array comprising a plurality of logic modules each logic module having two clusters, said logic modules arranged in rows and columns. The logic module clusters having a plurality of receiver components, a plurality of transmitter components, at least one buffer module, and at least one sequential logic components. Each logic module also comprises at least one left combinatorial logic unit having a carry-in input and carry-out output and at least one right combinatorial logic unit having a carry-in input and carry-out output adjacent to said left combinatorial logic unit. The carry-out output of the left combinatorial unit is hardwired to the carry-in input of said right combinatorial logic unit providing dedicated carry-in/carry-out logic circuitry.

Abstract: A novel fuzzy logic secondary voltage controller based on polar fuzzy logic rule is designed in this paper. The controller uses the voltage of the pilot node as a feedback signal and adjusts voltage level of the pilot node through the excitation control with the rules of fuzzy logic. The parameter regulation, performance and principle of the controller are briefly analyzed. The controller effectively combines fuzzy logic rule with secondary voltage control: the voltage error of pilot nodes and its differential are the front input of a fuzzy logic block. The regional voltage control signal is generated after a PI block, whose input is the voltage control signal which is obtained by the fuzzy logic rule. By using participant factor the generators' reactive power output in an area can be coordinated with each other. Numerical simulation is carried out on the New England 39 node system. Simulation of small disturbance on load shows that the fuzzy logic controller can restore the voltage level more rapidly than conventional controllers. When load increases slowly, the test system with fuzzy logic secondary voltage controller has a better voltage level and a larger steady voltage stability margin than those with conventional secondary voltage controllers.

Abstract: Modeling a logic design includes displaying a menu comprised of different types of functional block diagrams, receiving an input selecting one of the different types of functional block diagrams, retrieving a selected functional block diagram, and creating a graphical representation of a logic design using the selected functional block diagram. The graphical representation is created by interconnecting the selected functional block diagram with one or more other functional block diagrams to generate a model of a logic design and defining the selected functional block diagram using simulation code if the functional block diagram is undefined when retrieved.

Abstract: This paper presents design of a programmable fuzzy logic controller and its implementation on a complex programmable logic device (CPLD) chip. This digital fuzzy logic controller (FLC) can be reconfigured in term of its antecedents or membership function parameters, fuzzy implication rules, and consequence parameters. Due to its programmable capability, this digital FLC is intended to be a general-two-dimensional fuzzy controller for several application areas. The digital FLC circuit is designed to be as flexible as possible, and thus the user finds it easy to utilize the FLC in control applications, which need real-time operations. The digital FLC is implemented on a CPLD chip using a VHDL-based synthesis model.

Abstract: The object of the invention is to provide a software component ( 1, 2, 3 ) for a distributed control system having application units ( 4, 5 ) which have one or more logic function nodes which each define an individual control system function in the application units and interact with one another, or can interact with one another, in order to achieve a desired functionality for the control system; having a function means for implementation of a logic function node; a negotiation means for receiving a connection instruction relating to a connection to be set up to at least one further function node and for agreeing upon possible usable connection parameters between the function node and the at least one further function node during a composition phase of the control system; and a connection means for setting the negotiated connection parameters between the function means and for data transmission between the connected function means during a runtime of the control system.

Abstract: A method of generating a function within a logic design of a circuit, includes representing the function using an operator. The function has n operands, where n>1. The method also includes presenting the function within a schematic representation of the logic design. Other features may include displaying a dialog box and inputting data that corresponds to the function.

Abstract: A FIFO memory system for multiple input channels, has a channel control logic coupled to a channel input signal. A pointer and flag logic block is coupled to an output of the channel control logic. A memory has an address bus coupled to the channel control logic and the pointer and flag logic.

Abstract: Techniques from digital signal processing (DSP) have been used to perform some of the problematic operations needed in a fuzzy logic controller. These techniques have enabled the development of circuits which are not only compact but also scalable, so that we do not suffer as high a rate of increase of the use of resources as for conventional circuits when the accuracy of the controller or the number of inputs or membership functions is increased. Circuits have been developed so that a complete, reprogrammable fuzzy logic controller can be fitted into a medium-sized FPGA.

Abstract: This paper presents a multi-layer fuzzy logic controller (MLFLC) which is suitable for multi-input-multi-output (MIMO) systems. The controller is made up of some multi-input- single-output (MISO) fuzzy logic controllers. Each MISO fuzzy logic controller consists of many single-input-single-output (SISO) fuzzy logic controller. The membership functions of the controller are of a complement type, it has a set of switching surface. The system is asymptotically stable if the scaling factors satisfy certain condition. Simulation experiments based on a two-links manipulator demonstrate the validity of the proposed algorithms.

Abstract: PROBLEM TO BE SOLVED: To realize a programming including execution control by branch conditions, without lowering the readability in the circumstance of Function Block Diagram (FBD) language programming. SOLUTION: The programming method has a constitution having following components; a FBD language program editing part 4a organized so as to enable drawing of dividing on a plurality of sheets, when a definition of a process logic of a Program Organization Unit (POU) is described on the sheets by operator's drawing operation using FBD language, a sheet executing condition setting part 8 which sets the sheet executing conditions of local variables used in each sheet, a program conversion part 6a which converts to a software 7a performing execution, only when the condition is realized evaluating the sheet executing condition just before the programmable controller executes the process part, corresponding to each sheet in the order based on symbol information and sheet-executing condition of the FBD language program. COPYRIGHT: (C)2003,JPO

Abstract: The extensive description of complex functionalities in function block systems, using hybrid modeling methods can be simplified by identifying an internal structure of these function blocks For that a formal model of ‘function block components’ is needed Witch such a model the internal structure of batch-oriented blocks and advanced control blocks as two typical examples for complex functionalities in process control engineering is seperated in unified and generic and typespecific describable components, whose dynamic behaviour runs from discrete to continous and frequently is hybrid

Abstract: Methods and structures for efficiently implementing an accumulator-based load-store CPU architecture in a programmable logic device (PLD). The PLD includes programmable logic blocks, each logic block including function generators that can be optionally programmed to function as lookup tables or as RAM blocks. Each element of the CPU is implemented using these logic blocks, including an instruction register, an accumulator pointer, a register file, and an operation block. The register file is implemented using function generators configured as RAM blocks. This implementation eliminates the need for time-consuming accesses to an off-chip register file or to a dedicated RAM block.

Abstract: A programmable pulse code modulation encoder comprises a programmable controller arranged to receive a digital signal input and a plurality of parallel analog signal inputs. The said programmable controller is arranged to digitize the parallel analog signal inputs and modulate them with the digital signal input. A system clock is included to provide clock signals. A counter circuit is connected to the programmable controller to provide interrupt signals under the control of the system clock. A shift register is connected to the programmable controller to receive modulated parallel digital signals corresponding to the parallel analog signal inputs to the programmable controller. The shift register is also connected to the counter and is arranged to function as a parallel to serial converter to provide a serial data stream output at an output terminal of the shift register.

Abstract: A method for manufacturing a programmable logic controller (PLC) module includes mounting at least one valve inside the PLC module and positioning at least one outlet line in flow communication with the valve.

Abstract: A programmable logic device has a plurality of levels of programmable logic modules with fixed interconnections. The outputs of a level connect to inputs of the next level of programmable logic modules. The first level is fed from a bank of memory elements and the inputs to this bank of memory elements are derived from the last level. Crossbar switches are optionally inserted between a carefully chosen pairs of levels.