Computer Aided Design

Abstract: The long-standing goal of computer aided design (CAD)/computer aided engineering (CAE) integration demands seamless interfaces between geometric design and engineering analysis/simulation tasks. The key challenge to this integration stems from the distinct and often incompatible roles geometric representations play, respectively, in design and analysis. This paper critically examines and compares known mesh-based and meshfree approaches to CAD/CAE integration, focusing on the basic tasks and components required for building fully integrated engineering applications. For each task, we identify the fundamental requirements and challenges and discuss how they may be met by known techniques and proposed solutions. [DOI: 10.1115/1.3593416]

Abstract: Topology optimization is an important topic in structural mechanics. One common application is to obtain the optimal distribution of material that maximizes the stiffness of the solution (minimize the compliance). However, as an iterative process, topology optimization of large and complex structures is computationally intensive. The problem becomes even more complicated if the manufacturing constraints are taken into account in the optimization process. In this paper, a novel growth method based on principal stress lines (PSLs) is presented for topology optimization. The PSLs are traced in the design domain along the direction of principal stresses, in which the materials would be located to define the geometry and topology of the structure. Consequently, the optimization problem is converted into a geometric design problem. Compared to previous methods, the computation based on PSLs is fast, and the designer can have explicit control over the number of structural members. In addition, the manufacturing constraints can easily be incorporated. Multiple test cases are given to illustrate the presented method. The PSL-based method is promising for building practical designing tools for various structural applications.

Abstract: The need for good design automation in the area of integrated circuit layout is severe. It is believed that the STICKS system does much to fill that need. STICKS is a computer aided design system which frees the designer from the tedious aspects of IC design and allows him to concentrate on the more creative and necessarily human side of the design process. With STICKS the designer is allowed to divorce himself from the usual precise sizes, spacings, and interrelationships required for an IC layout and, instead, submit his creativity in the form of rough, freehand sketches. The computer makes whatever adjustments are necessary in order to generate an error-free layout. The opportunity is then given to verify and, if necessary, modify the computer's interpretation of the design .. An interactive loop is thus formed with the computer doing all of the tedious, detailed work and the human designer providing the necessary inspiration. Using traditional' methods, large scale integrated circuit layout is a tedious, time consuming and error prone process. IC layout is a procedure which results in the placement and interconnection of each of the thousands of components which . form the integrated circuit. The designer accomplishes this by drawing several superimposed "mask" layers using a drafting board which together, control the areas where various chemical diffusions and etchings will be made on the silicon wafer that forms the IC. Components such as transistors, diodes, resistors, and their interconnections are formed by various combinations of these masked areas. Unfortunately, the specific sizes of and spacings between components is critical, preventing the designer's job from being an easy one. There is an overall goal in IC design to pack as much circuitry as possible into a small area. The more circuitry a particular IC contains, the more valuable it is and, consequently, the more marketable it is. The physical size of the chip, however, is a major factor constraining the number of components. Due to a parameter known as defect density, the larger the chip, the less likely it is to work and the more it will cost. Defect density is the number of random material defects per given area which result both from the starting silicon material and from normal losses in the manufacturing process. The solution, one would think, would be to simply make everything smaller thereby increasing component den-

Abstract: The paper describes an advanced demonstration system which brings together a number of recent developments in CAAD (computer-aided architectural design). This demonstration system illustrates how an important new form of input device, a 3D modelling systemm can be linked with building performance software and ‘indicative’ computer output graphics. The 3D modelling system uses electronically interrogable building elements. The user assembles these elements on a baseboard, providing a tangible model of the design. The model is then interrogated by the CAD system, which recovers the geometry data describing the topology of the model. The user changes the design by reassembling the model elements. A particular aspect of this demonstration is that the user has the option to generate building design data and assimilated building performance data without the need to handle this data in numeric form. It is likely that many of the features present in this demonstration system will be evident in future ‘production’ CAAD systems.