Topic
Clock generator
About: Clock generator is a research topic. Over the lifetime, 7245 publications have been published within this topic receiving 58042 citations.
Papers published on a yearly basis
1 / 2
Papers
Patent•
27 Oct 2005TL;DR: In this article, a DLL system includes a phase detector coupled to an input signal for generating a first phase error signal according to the input signal and a clock signal, an up-down counter coupled to the phase detector for counting the first phase errors, and an adder coupled to a sigma-delta modulator for summing the first and second phase errors according to a reference clock.
Abstract: A DLL system includes a phase detector coupled to an input signal for generating a first phase error signal according to the input signal and a clock signal; an up-down counter coupled to the phase detector for generating a counting signal according to the first phase error signal; a sigma-delta modulator (SDM) coupled to the up-down counter for generating a second phase error signal according to the counting signal; an adder coupled to the SDM and the phase detector for summing the first phase error signal and the second phase error signal to generate a sum signal; a clock generator for generating a plurality of candidate clock signals according to a reference clock; and a multiplexer coupled to the clock generator and the phase detector for selecting one of the candidate clock signals to be the clock signal inputted into the phase detector according to the sum signal.
15 citations
Patent•
9 May 2006TL;DR: In this article, a tunable low power clock generator employs a voltage regulator, one or current generators and a variable resistor bank that, together, produce a control voltage for trimming a VCO.
Abstract: A tunable, low power clock generator employs a voltage regulator, one or current generators and a variable resistor bank that, together, produce a control voltage for trimming a VCO. The control voltage is arranged to also compensate, at least, for the variables of temperature, supply voltage and fabrication processes as they affect the VCO output frequency. The current generator is well characterized over the variables discussed and the resistor bank is a flexible series/parallel array of resistors made from differing materials exhibiting different temperature coefficients. The resistor bank provides for various overlapping resistance values simultaneously with various overlapping temperature coefficients wherein the temperature coefficient profile of the clock generator over frequency and temperature is controlled.
15 citations
Patent•
16 Feb 2000
TL;DR: In this article, a plurality of intermediate driving devices are included in stages between a clock generator and a bank of synchronous logic devices, and the outputs of the intermediate devices in each stage are connected in parallel over a wide linear dimension.
Abstract: A plurality of intermediate driving devices are included in stages between a clock generator and a bank of synchronous logic devices. The outputs of the intermediate devices in each stage are connected in parallel over a wide linear dimension. The timing delay of each circuit is then subject to a small variation depending on the irregularities associated with the device characteristics used in its construction. The outputs of the intermediate devices in each stage are tied together to restore regularity and uniformity to all clock generation circuit outputs.
15 citations
Patent•
19 Jun 1991
TL;DR: In this paper, a computer system is made capable of accepting more than one type of central processor including a plurality of sockets for receiving more than a single identification signal, a clock generator responsive to said identifying signal for generating clock signals for the identified type of processor, and means responsive to identified signal for disabling and enabling signal paths from the socket.
Abstract: A computer system is made capable of accepting more than one type of central processor including a plurality of sockets for receiving more than one type of identification signal, a clock generator responsive to said identifying signal for generating clock signals for the identified type of processor, and means responsive to said identifying signal for disabling and enabling signal paths from the socket.
15 citations
IBM1
TL;DR: In this article, a new test structure is developed, which is comprised of MOSFET arrays and an on-chip operational amplifier feedback loop for measuring threshold voltage variation, which can be used in an inline test environment to provide rapid assessment of Vt variation for technology development and chip manufacturing.
Abstract: A new test structure has been developed, which is comprised of MOSFET arrays and an on-chip operational amplifier feedback loop for measuring threshold voltage variation. The test structure also includes an on-chip clock generator and address decoders to scan through the arrays. It can be used in an inline test environment to provide rapid assessment of Vt variation for technology development and chip manufacturing. Hardware results in a 65 nm technology are presented.
15 citations
Related Topics (5)
Performance Metrics
| Year | Papers |
|---|---|
| 2025 | 7 |
| 2024 | 7 |
| 2023 | 19 |
| 2022 | 33 |
| 2021 | 64 |
| 2020 | 147 |