Topic
Block (data storage)
About: Block (data storage) is a research topic. Over the lifetime, 33998 publications have been published within this topic receiving 372145 citations. The topic is also known as: data block & logical block.
Papers published on a yearly basis
1 / 2
Papers
Patent•
30 Jan 1981TL;DR: In this article, an encoder and decoder are separated into two independent list decoders, a comparator, and common clock generator and output buffers, each list decoder is divided into a syndrome generator and an overall parity check generator, a syndrome error pattern table, an input buffer, error correction logic, and four-error detection logic.
Abstract: A codec consists of an encoder and decoder. The encoder provides 12 information bits, 11 parity bits generated according to the polynomial for the (23, 12) Golay code, and an overall parity bit to a transmitter at selected transmit times to form a 24-bit block of data. The decoder is separated into two independent list decoders, a comparator, and common clock generator and output buffers. Each list decoder is divided into a syndrome generator and an overall parity check generator, a syndrome error pattern table, an input buffer, error correction logic, and four-error detection logic. The error pattern table includes a pair of read only memories storing the most likely 12-bit error patterns at each ROM address corresponding to each syndrome. An additional 4-bit output is used to indicate the number of errors in the associated error pattern. The comparator compares the number of errors detected in the two independent decoders and chooses the decoder having the fewer number of errors to provide the corrected data.
88 citations
Patent•
10 Apr 2013
TL;DR: In this article, a plurality of data structures corresponding to levels of indirection are used to manage the mapping between a user logical block address and the physical location of the data in the flash memory system.
Abstract: A method and system for managing a flash memory system facilitates the use of TRIM or similar operations so as to release physical memory space of logical block addresses (LBAs) that are declared to be deleted by a user file management system. A plurality of data structures corresponding to levels of indirection are used to manage the mapping between a user logical block address and the physical location of the data in the flash memory system and to respond to user read and write requests by determining the current status of the user logical block address in the frame of reference of the memory system. This process substantially decouples TRIM management from garbage collection and wear leveling operations.
88 citations
Patent•
12 Oct 2007
TL;DR: In this article, a RAM mapping table is restored from flash memory using plane, block, and page addresses generated by a physical sequential address counter using interleaved bits extracted from the lowest bits of the logical block index.
Abstract: A RAM mapping table is restored from flash memory using plane, block, and page addresses generated by a physical sequential address counter. The RAM mapping table is restored following a plane-interleaved sequence generated by the physical sequential address counter using interleaved bits extracted from the lowest bits of the logical block index. These plane-interleave bits are split into a LSB and a MSB, with middle physical block bits between the LSB and MSB. The physical sequential address counter generates a physical block number by incrementing the plane-interleave bits before the middle physical block bits, and then relocating the MSB to above the middle physical block bits. This causes blocks to be accessed in a low-high sequence of 0, 1, 4096, 4097, 2, 3, 4098, 4099 , etc. in the four planes of flash memory. Background recycling and ECC writes are also performed.
88 citations
26 Jun 2004
TL;DR: The standard is carefully analyzed in order to point out the parts where it is non-exhaustive and a set of implementation approaches is investigated underlying advantages and disadvantages of each solution.
Abstract: The paper presents different approaches to implement the execution model of an IEC 61499 application. The IEC 61499 standard defines the application as a function block network whose nodes are function blocks and whose branches are data/event connections. The standard provides also the execution model for a basic FB and the behavior of an instance, but these specifications are not exhaustive. Consequently, there may be many different implementations of the execution model that are all compliant with the standard but produce different behaviors. In this work, the standard is carefully analyzed in order to point out the parts where it is non-exhaustive. Furthermore, a set of implementation approaches is investigated underlying advantages and disadvantages of each solution
88 citations
TL;DR: An efficient and interactive two-stage heuristic for the generation of block layouts is presented, which generates a hexagonal and maximum weight planar adjacency subgraph, which incorporates relationships with the outside of the layout in a consistent manner.
88 citations
Related Topics (5)
Performance Metrics
| Year | Papers |
|---|---|
| 2022 | 22 |
| 2021 | 1,478 |
| 2020 | 2,424 |
| 2019 | 3,007 |
| 2018 | 2,222 |
| 2017 | 1,759 |