Patent
Tunable delay circuit
Paul A. Silvestri
- 16 May 2002
15
TL;DR: In this paper, a delay-locked loop with a forward path for receiving an input signal to provide an output signal, a feedback path for providing a feedback signal based on the output signal and a controller responsive to a timing relationship between the feedback signal and the input signal is presented.
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Abstract: A delay locked loop includes a forward path for receiving an input signal to provide an output signal, a feedback path for providing a feedback signal based on the output signal, and a controller responsive to a timing relationship between the feedback signal and the input signal for adjusting a timing of the output signal. The feedback path includes an adjustable delay circuit for adjusting a timing of the feedback signal.
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Citations
Patent
Delay locked loop with frequency control
Debra M. Bell,Paul A. Silvestri +1 more
- 16 May 2002
TL;DR: In this article, a delay controller controls the delay line to keep the external and internal signals synchronized, and a cycle control circuitry for controlling the cycle time of the signal entering the delay and the cycle times exiting the delay.
26
Patent
Graduated delay line for increased clock skew correction circuit operating range
Tyler J. Gomm,Gary M. Johnson +1 more
- 19 May 2005
TL;DR: In this article, the authors describe clock synchronization and skew adjustment circuits that utilize varying unit delay elements in their delay lines in either a graduated or a stepped unit time delay arrangement, allowing a reduced circuit implementation and improved lock characteristics.
25
Patent
Measure-controlled circuit with frequency control
Tyler J. Gomm,Debra M. Bell +1 more
- 30 Nov 2006
TL;DR: A delay-locked circuit has multiple paths for receiving an external signal, one path measures a timing of the external signal during a measurement and the other path generates an internal signal based on the external signals.
17
Patent
Delay Lock Loop Delay Adjusting Method and Apparatus
Adrian E. Ong,Douglas W. Gorgen +1 more
- 10 Sep 2007
TL;DR: In this article, the propagation time is used to determine an initial delay value within a delay lock loop, which is then changed until a preferred delay value, resulting in synchronization, is found.
16
Patent
Bias generator with feedback control
Feng Lin
- 29 Jul 2005
TL;DR: In this article, a bias generator is used for initializing a voltage controlled delay line by providing the voltage controlled line with a control signal having an initial voltage and monitoring the variable delay line for an output clock signal.
13
References
Patent
Pre-divider architecture for low power in a digital delay locked loop
Timothy Fiscus
- 30 Mar 2001
TL;DR: In this paper, a delay-locked loop circuit for conserving power on a semiconductor chip is presented, where a pre-divider circuit is configured to disable the delay chain circuit when the output clock signal is inactive and the memory device is in an idle state.
44
Patent
Clock delay circuitry producing clock delays less than the shortest delay element
Ishimi Kouichi,Kazuyuki Ishikawa +1 more
- 21 May 1998
TL;DR: In this article, a phase comparator compares the phase of a signal associated with a delay loop to that of a reference clock signal, generating a phase difference clock signal and a delay setting circuit can cause the selector to change the selection of one delayed clock signal according to the phase difference signal from the phase comparators.
42
Patent
Compensation for a delay locked loop
Eric T. Stubbs,Christopher K. Morzano +1 more
- 14 Jul 2000
TL;DR: In this article, a delay line of a delay-locked loop is disclosed, the delay line having a plurality of delay elements and a minimum and maximum delay boundary, and the artificial boundaries become transparent to the delay element and are available for the circuitry to use if needed.
35
Patent
Method and apparatus for characterizing a delay locked loop
Tyler J. Gomm,Michael B. Roth +1 more
- 29 Jun 2004
TL;DR: In this article, a delay-locked loop consisting of a forward path, a feedback path, phase detector, logic, and a dither circuit is presented. But the phase detector is not in phase with the input clock signal.
33
Patent
Timing control for input/output testability
Gregory F. Taylor
- 24 Dec 1997
TL;DR: In this article, the phase difference between a strobe signal and a delayed signal is measured in a delayed-lock loop (DLL) in either a transmitter (driver) or a receiver.
31