Patent
Transistor with embedded Si/Ge material having reduced offset and superior uniformity
Stephan Kronholz,Peter Javorka,Roman Boschke +2 more
- 13 Jan 2011
21
TL;DR: In this paper, a strain-inducing embedded semiconductor alloy is provided on the basis of a crystallographically anisotropic etch process and a self-limiting deposition process, where transistors which may not require an embedded strain inducing alloy may remain non-masked, thereby providing superior uniformity with respect to overall transistor configuration.
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Abstract: In sophisticated semiconductor devices, a strain-inducing embedded semiconductor alloy may be provided on the basis of a crystallographically anisotropic etch process and a self-limiting deposition process, wherein transistors which may not require an embedded strain-inducing semiconductor alloy may remain non-masked, thereby providing superior uniformity with respect to overall transistor configuration. Consequently, superior strain conditions may be achieved in one type of transistor, while generally reduced variations in transistor characteristics may be obtained for any type of transistors.
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Citations
Patent
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TL;DR: In this article, a semiconductor structure and a method of fabricating the semiconductor structures are provided, which includes a substrate, a metal gate structure on the substrate, and a spacer next to the metal gate with a skirting part extending into the gate structure and contacting the substrate.
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- 19 Feb 2015
TL;DR: In this paper, a semiconductor device including source drain stressors and methods of manufacturing the same are provided, including forming a recess region in the substrate at a side of a gate pattern, and an inner surface of the recess region may include a first surface of a (100) crystal plane and a second surface of one of {111} crystal planes.
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Semiconductor structure and method for manufacturing the same
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- 03 Jul 2012
TL;DR: In this article, a semiconductor device structure and a method for manufacturing the same is presented, wherein the method comprises: forming the semiconductor substrate comprising a local SOI structure having a local buried isolation dielectric layer; forming a fin on the silicon substrate on top of the local buried IC layer; form a gate stack structure on the top and side faces of the fin; forming source/drain structures in the fin on both sides of the gate stack; and performing metallization.
14
References
Patent
Method for improving transistor performance through reducing the salicide interface resistance
Anand S. Murthy,Boyan Boyanov,Glenn A. Glass,Thomas Hoffmann +3 more
- 29 Jun 2005
TL;DR: In this article, a silicon germanium alloy was used to form the contact surface of the source and drain regions of a transistor, which reduced the external resistance of the transistor by using a nickel silicon-germanium self-aligned silicide layer.
94
Patent
MOS Devices with Partial Stressor Channel
Ming-Hua Yu,Mong-Song Liang,Tze-Liang Lee,Jr.-Hung Li +3 more
- 06 Jan 2011
TL;DR: In this article, a semiconductor structure is defined, and a stressor has a tilted sidewall on a side adjacent the gate electrode and a second layer has a third lattice constant substantially different from the first and the second lattice constants.
92
Patent
Method and structure to prevent silicide strapping of source/drain to body in semiconductor devices with source/drain stressor
Yung Fu Chong,Brian J. Greene +1 more
- 16 Jul 2005
TL;DR: In this paper, the authors disclose devices and methods to prevent silicide strapping of the Source/Drain to Body (S/D) in semiconductor devices with S/D stressor.
56
Patent
Epitaxial silicon germanium for reduced contact resistance in field-effect transistors
Lucian Shifren,Jack T. Kavalieros,S. Cea,Cory E. Weber,Justin K. Brask +4 more
- 31 Mar 2006
TL;DR: In this paper, a method for selectively relieving channel stress for n-channel transistors with recessed, epitaxial SiGe source and drain regions is described, where the SiGe provides lower resistance when a silicide is formed.
40
Patent
Semiconductor devices having faceted silicide contacts, and related fabrication methods
Frank Bin Yang,Rohit Pal,Michael J. Hargrove +2 more
- 10 Oct 2008
TL;DR: In this article, the authors describe the fabrication of semiconductor transistor devices and associated fabrication techniques that can be utilized to form silicide contacts having an increased effective size, relative to conventional silicide contact.
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