Patent
Speculative load instructions with retry
Andrew Johnson
- 10 Jan 2002
15
TL;DR: In this paper, a system, method and apparatus is provided that splits a microprocessor load instruction into two (2) parts, a speculative load instruction and a check speculative load instructions, which can be moved ahead by the compiler as soon as the address and result registers are available.
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Abstract: A system, method and apparatus is provided that splits a microprocessor load instruction into two (2) parts, a speculative load instruction and a check speculative load instruction. The speculative load instruction can be moved ahead in the instruction stream by the compiler as soon as the address and result registers are available. This is true even when the data to be loaded is not actually required. This speculative load instruction will not cause a fault in the memory if the access is invalid, i.e. the load misses and a token bit is set. The check speculative load instruction will cause the speculative load instruction to be retried in the event the token bit was set equal to one. In this manner, the latency associated with branching to an interrupt routine will be eliminated a significant amount of the time. It is very possible that the reasons for invalidating the speculative load operation are no longer present (e.g. page in memory is not present) and the load will be allowed to complete. Therefore, substantial gains in efficiency and resource utilization can be achieved by deferring the branch to recovery routines until after the speculative load is retried.
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Citations
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References
Patent
Forwarding stored dara fetched for out-of-order load/read operation to over-taken operation read-accessing same memory location
Michael K. Gschwind
- 03 Feb 1999
TL;DR: In this paper, the authors present a method for scheduling instructions for execution in a computer processing system implementing out-of-order execution, which includes the steps of selecting and moving a next instruction from its current position in a sequence of instructions to an earlier position.
50
Patent
Apparatus for executing coded dependent instructions having variable latencies
Ramesh Panwar,Ricky C. Hetherington +1 more
- 25 Jun 1997
TL;DR: In this article, a processor that executes coded instructions using an instruction scheduling unit receiving the coded instructions and issuing an instruction for execution is shown a signal indicating when the instruction failed to execute properly within a predetermined time.
48
Patent
Method and apparatus for executing load instructions speculatively
Kent Fielden
- 14 Sep 1998
TL;DR: In this paper, a load may be executed speculatively while ensuring that an exception occurs at the same time it would have occurred had the load been executed non-speculatively, and a check instruction which when executed determines whether an exception should be taken on the dismissible load.
41
Patent
Method and apparatus for advancing load operations
Judge K. Arora,Gregory S. Mathews,Ghassan Khadder,Sreenivas A. Reddy +3 more
- 31 Dec 1999
TL;DR: In this article, a computer is made to replace a load instruction at a particular location in a computer program instruction sequence with two instructions, an advanced load instruction and a load check instruction.
39
Patent
Multiprocessor speculation mechanism with imprecise recycling of storage operations
Guy Lynn Guthrie,Ravi Kumar Arimilli,John Steven Dodson,Derek Edward Williams +3 more
- 06 Jun 2000
TL;DR: Disclosed as mentioned in this paper is a method of operating a processor, by which a speculatively issued load request, which fetches incorrect data, is recycled by using a pre-determined type of invalidate, which is affiliated with the load request.
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