Proceedings Article10.1145/2228360.2228546
Small delay testing for TSVs in 3-D ICs
Shi-Yu Huang,Yu-Hsiang Lin,Kun-Han Tsai,Wu-Tung Cheng,Stephen Sunter,Yung-Fa Chou,Ding-Ming Kwai +6 more
- 03 Jun 2012
- pp 1031-1036
65
TL;DR: A robust small delay test scheme for through-silicon vias (TSVs) in a 3D IC is presented by changing the output inverter's threshold of a TSV in a testable oscillation ring structure, and thereby detecting a small delay fault.
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Abstract: In this work, we present a robust small delay test scheme for through-silicon vias (TSVs) in a 3D IC By changing the output inverter's threshold of a TSV in a testable oscillation ring structure, we can approximate the propagation delay across that TSV, and thereby detecting a small delay fault SPICE simulation reveals that this Variable Output Thresholding (VOT) technique is still effective even when there is significant process variation in detecting a slow TSV with some resistive open defect that may escape the traditional at-speed test
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Citations
Non-invasive pre-bond TSV test using ring oscillators and multiple voltage levels
Sergej Deutsch,Krishnendu Chakrabarty +1 more
- 18 Mar 2013
TL;DR: This work proposes a non-invasive method for pre-bond TSV test that does not require TSV probing and can detect resistive open and leakage faults.
49
Parametric Delay Test of Post-Bond Through-Silicon Vias in 3-D ICs via Variable Output Thresholding Analysis
Yu-Hsiang Lin,Shi-Yu Huang,Kun-Han Tsai,Wu-Tung Cheng,Stephen Sunter,Yung-Fa Chou,Ding-Ming Kwai +6 more
TL;DR: By dynamically switching the output of a TSV from a normal inverter to a Schmitt-Trigger inverter, the parametric delay fault on the TSV can be characterized and detected and SPICE simulation reveals that this technique remains effective even when there is significant process variation.
40
Online Fault Tolerance Technique for TSV-Based 3-D-IC
TL;DR: This brief presents the design, validation, and evaluation of an efficient online fault tolerance technique for fault detection and recovery in presence of three through-silicon-vias (TSV) defects.
38
Thermal-Aware Small-Delay Defect Testing in Integrated Circuits for Mitigating Overkill
TL;DR: This paper quantifies, for the first time, the impact of thermal emergencies on small-delay defects (SDDs) and provides a solution to mitigate them and demonstrates that the new method can significantly reduce the number of over-detections of SDDs.
32
TSV Extracted Equivalent Circuit Model and an On-Chip Test Solution
Zheng Gong,Rashid Rashidzadeh +1 more
TL;DR: A new method utilizing computer-aided design tools to extract circuit models for prebond and postbond TSVs is presented, indicating that even a relatively large void does not alter the TSV characteristic parameters and thus voids remain largely undetected with conventional test solutions.
31
References
Electrical Modeling and Characterization of Through Silicon via for Three-Dimensional ICs
TL;DR: In this paper, the RLC parameters of the TSV are modeled as a function of physical parameters and material characteristics, and a TSV RLC model is applied to predict the resistance, inductance, and capacitances of small-geometry TSV architectures.
Testing 3D chips containing through-silicon vias
Erik Jan Marinissen,Yervant Zorian +1 more
- 18 Dec 2009
TL;DR: This Embedded Tutorial provides an overview of the manufacturing steps of TSV-based 3D chips and their associated test challenges, and discusses the necessary flows for wafer-level and package-level tests, the challenges with respect to test contents and wader-level probe access, and the on-chip DfT infrastructure required for 3D-SICs.
347
Modeling the driving-point characteristic of resistive interconnect for accurate delay estimation
P.R. O'Brien,T.L. Savarino,T.L. Savarino +2 more
- 05 Nov 1989
TL;DR: In this paper, a reduced-order approximation for the Taylor series expansion coefficients of the driving-point admittance of an RC tree is presented. But this algorithm is not suitable for the case of series resistance.
263
On-Chip TSV Testing for 3D IC before Bonding Using Sense Amplification
Po-Yuan Chen,Cheng-Wen Wu,Ding Ming Kwai +2 more
- 23 Nov 2009
TL;DR: A novel testing scheme for TSVs in a 3D IC is presented by performing on-chip TSV monitoring before bonding, using a sense amplification technique that is commonly seen on a DRAM.
158
Performance Characterization of TSV in 3D IC via Sensitivity Analysis
Jhih-Wei You,Shi-Yu Huang,Ding-Ming Kwai,Yung-Fa Chou,Cheng-Wen Wu +4 more
- 01 Dec 2010
TL;DR: A technique called sensitivity analysis is proposed to derive the propagation delay of each individual TSV participating in the oscillation ring – a distilling process to characterize the propagation delays across the Through Silicon Vias in a 3D IC.
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