Simulation based test generation for scan designs
Irith Pomeranz,Sudhakar M. Reddy +1 more
- 05 Nov 2000
- pp 544-549
10
TL;DR: The proposed procedure constructs test sequences that traverse as many pairs of fault-free/faulty states as possible, and thus avoids the use of branch-and-bound test generation techniques.
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Abstract: We describe a simulation-based test generation procedure for scan designs. A test sequence generated by this procedure consists of a sequence of one or more primary input vectors embedded between a scan-in operation and a scan-out operation. We consider the set of faults that can be detected by test sequences of this form, compared to the case where scan is applied with every test vector. The proposed procedure constructs test sequences that traverse as many pairs of fault-free/faulty states as possible, and thus avoids the use of branch-and-bound test generation techniques. Additional techniques are incorporated into this basic procedure to enhance its effectiveness.
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Citations
Transparent scan: a new approach to test generation and test compaction for scan circuits that incorporates limited scan operations
Irith Pomeranz,Sudhakar M. Reddy +1 more
TL;DR: A new approach to test generation and test compaction for scan circuits that eliminates the distinction between scan operations and application of primary input vectors is described, resulting in test sequences with the lowest known test application times for benchmark circuits.
31
Comprehensive frequency-dependent substrate noise analysis using boundary element methods
Hongmei Li,Jorge Carballido,Harry H. Yu,Vladimir Okhmatovski,Elyse Rosenbaum,Andreas C. Cangellaris +5 more
- 10 Nov 2002
TL;DR: In this article, a new and efficient method is introduced for the calculation of the Green's function that can accommodate arbitrary substrate doping profiles and thus facilitate substrate noise analysis using boundary element methods.
On pass/fail dictionaries for scan circuits
I. Pomeranz
- 19 Nov 2001
TL;DR: A dictionary enhancement method is described that allows all the fault pairs distinguishable by a full fault dictionary to be distinguished by the enhanced pass/fail dictionary.
23
A New Approach to Test Generation and Test Compaction for Scan Circuits
Irith Pomeranz,Sudhakar M. Reddy +1 more
- 03 Mar 2003
TL;DR: A new approach to test generation and test compaction for scan circuits that eliminates the distinction between scan operations and application of primary input vectors is proposed, resulting in test sequences with the lowest known test application times for benchmark circuits.
20
A storage-based built-in test pattern generation method for scan circuits based on partitioning and reduction of a precomputed test set
Irith Pomeranz,Sudhakar M. Reddy +1 more
TL;DR: The effectiveness of the proposed built-in test pattern generation method for scan circuits as a stand-alone procedure and as part of a scheme where random patterns are first applied to detect easy-to-detect faults is demonstrated.
19
References
Simulator-oriented fault test generator
Thomas J. Snethen
- 01 Jan 1977
TL;DR: This paper describes a method of test pattern generation that was developed with three objectives: to generate long pattern sequences systematically when needed, to model the sequential logic accurately so that any test generated would be valid, and to focus on assumed faults such as stuck 1 and stuck 0.
52
LOCSTEP: a logic simulation based test generation procedure
Irith Pomeranz,Sudhakar M. Reddy +1 more
- 27 Jun 1995
TL;DR: It is shown that when deterministic test sequences are applied, the fault free circuits go through sequences of state transitions that have distinct characteristics which are independent of the specific circuit considered.
51
Random pattern testing for sequential circuits revisited
Lama Nachman,Kewal K. Saluja,S. Upadyaya,R. Reuse +3 more
- 25 Jun 1996
TL;DR: The algorithm consists of simulating a sequential circuit systematically, possibly with partial scan, in conjunction with the hold method, and is very effective in providing fault coverage close to the maximum obtainable fault coverage using random patterns with full scan.
47
Iterative [simulation-based genetics + deterministic techniques]= complete ATPG0
Daniel G. Saab,Youssef G. Saab,Jacob A. Abraham +2 more
- 06 Nov 1994
TL;DR: This paper proposes a correction technique for simulation-based ATPG based on identifying the diverging state and on computing a fault cluster (faults close to each other) which has been used to generate tests with very high fault coverage.
46
LOCSTEP: a logic-simulation-based test generation procedure
Irith Pomeranz,Sudhakar M. Reddy +1 more
TL;DR: It is shown that when deterministic test sequences are applied, the fault-free circuits go through sequences of state transitions that have distinct characteristics which are independent of the specific circuit considered.
40
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