Patent
Semiconductor memory structure and method for preparing the same
Liao Wei-Ming
- 01 Mar 2019
1
TL;DR: In this paper, the authors provided a semiconductor memory structure including a substrate including a first isolation structure and at least one active region defined by the first isolations structure, a second isolation structure disposed in the active region, a first buried word line and a second buried digit line disposed in an isolation structure.
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Abstract: The present disclosure provides a semiconductor memory structure including a substrate including a first isolation structure and at least one active region defined by the first isolations structure, a second isolation structure disposed in the active region, a first buried word line and a second buried word line disposed in the second isolation structure, and at least one buried digit line disposed in the active region. Topmost portions of the first buried word line and the second buried word line are lower than a top surface of the second isolation structure, and a top surface of the buried digit line is lower than bottom surfaces of the first buried word line and the second buried word line.
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Citations
Patent
Dyanmic random access memory and method of manufacturing the same
Lin Chang-Hung,Chang Feng-Jung,Ouyang Tzu-Ming +2 more
- 21 Aug 2020
TL;DR: In this article, the substrate and the hard mask are partially removed to form a plurality of isolation trenches extending in the first direction and arranged in the second direction, and to define the plurality of active regions.
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Transistor array for semiconductor memory devices and method for fabricating a vertical channel transistor array
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TL;DR: In this paper, a transistor array for semiconductor memory devices is provided, where a plurality of semiconductor pillars extending outwardly from a bulk section of a semiconductor substrate is arranged in rows and columns.
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Patent
Semiconductor device with vertical transistor and method for fabricating the same
Jong-Han Shin
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TL;DR: In this paper, a semiconductor device with a vertical transistor includes a plurality of active nodes, including active columns, active gates surrounding sidewalls of the active nodes and word lines having exposed sidewalls whose surfaces are higher than active nodes.
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Patent
Semiconductor device with buried bit lines and method for fabricating the same
Su-Young Kim
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TL;DR: A semiconductor device includes a semiconductor substrate configured to include a plurality of trenches, a set of buried bit lines, vertical gates, and vertical gates with each other.
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