Patent
Semiconductor memory device invalidating improper control command
Jun Setogawa
- 06 Jul 2005
7
TL;DR: In this paper, a control circuit in a semiconductor memory device accessing a memory cell for a plurality of cycles includes an internal command generating circuit and a mask signal generating circuit, each of which outputs an internal signal instructing an operation to access the memory cell at H level when the mask signal is at L level, because a latch circuit is reset.
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Abstract: A control circuit in a semiconductor memory device accessing a memory cell for a plurality of cycles includes an internal command generating circuit and a mask signal generating circuit. Upon receiving a control command, the internal command generating circuit outputs an internal signal instructing an operation to access the memory cell at H level when a mask signal is at L level, while outputs an internal signal at L level when the mask signal is at H level, because a latch circuit is reset. The mask signal generating circuit outputs the mask signal at H level for a following cycle, when the internal signal is output at H level.
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Citations
Patent
Semiconductor memory device and read wait time adjustment method thereof, memory system, and semiconductor device
Atsuo Koshizuka
- 23 Jan 2013
TL;DR: In this paper, a controller includes a set of first terminals to be coupled to a device that is under control of the controller, and a control circuit configured to generate and output onto the set of the first terminals synchronous mode information including a selected one of selection and non-selection modes.
15
Patent
Semiconductor memory device having test mode for data access time
Ji-Eun Jang,Kee-Teok Park +1 more
- 28 Dec 2004
TL;DR: In this paper, a pipe latch control unit for measuring data access time by controlling data output operation, including a test mode signal and an output unit for controlling an output data outputted from the pipe latch means according to the CAS latency in synchronization with the clock signal at the normal mode or passing the output data without synchronization at the test mode based on the output node control signal.
9
Patent
Semiconductor memory, memory controller and control method for semiconductor memory
Eto Satoshi,Kuninori Kawabata,Miyo Toshiya,Serizawa Yuji +3 more
- 22 May 2006
TL;DR: Semiconductor memory for inputting and outputting data synchronously with a clock, comprising: a clock reception unit for receiving the clock; and a command reception unit, for initially receiving a first specific command synchronizing with the clock after turning a power on, after a low-power standby or after an initialization, followed by starting an initialization as mentioned in this paper.
7
Patent
Efficient register for additive latency in DDR2 mode of operation
Jon Allan Faue,Craig Barnett +1 more
- 03 Mar 2005
TL;DR: An additive latency circuit for a DDR2 standard compliant integrated circuit memory includes a half flip-flop register assigned for each case of additive latency, and a unique clock is generated to control each bit in the register chain this paper.
5
Patent
Memory system that handles access to bad blocks
Nobuhiro Tsuji,Kada Kenichirou,Shinya Takeda,Toshihiko Kitazume,Shunsuke Kodera,Iwata Tetsuya,Yoshio Furuyama,Hirosuke Narai +7 more
- 04 Mar 2016
TL;DR: In this article, a memory system includes a plurality of pins for connection to the outside of the memory system, one of the pins being configured to receive a command signal, a memory cell array including a first memory block and a second memory block in which status data indicating which of the first memory blocks is defective, is stored, and a control circuit configured to determine whether or not a target memory block is indicated as being defective in the status data.
3
References
Patent
Clock synchronous semiconductor memory device having a reduced access time
Tsukasa Ooishi
- 21 Dec 1999
TL;DR: In this paper, the first internal control pulse produced for the operation mode is made different from those for the subsequent control pulses, and a data access time after application of a row access command is reduced.
66
Patent
Multibank-multiport memories and systems and methods using the same
Mohan G.R. Rao
- 13 Jun 1997
TL;DR: A memory comprising a first memory bank and a second memory bank as discussed by the authors includes a plurality of data input/output terminals, including a first subset of the plurality for accessing the first memory banks, a second subset of data inputs and outputs for accessing the second memory banks.
23
Patent
Synchronous semiconductor memory device and method for controlling mask data input circuit
Shinichiro Ikeda
- 30 Aug 2001
TL;DR: In this paper, a method for controlling an input circuit of a synchronous semiconductor memory device that reduces current consumption without changing commands or increasing signal input terminals is presented, where the input circuit is activated and the mask control signal is invalidated.
8
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