Patent
Semiconductor memory device
Ohno Takashi,Doi Hitoshi +1 more
- 13 Feb 2001
25
TL;DR: In this paper, the problem of constructing a chip ID circuit and a roll call circuit in a semiconductor memory device without increasing a layout area is addressed. But the problem is not addressed in this paper.
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Abstract: PROBLEM TO BE SOLVED: To form a chip ID circuit and a roll call circuit in a semiconductor memory device without increasing a layout area. SOLUTION: This device 10 is provided with determination means 18 and 19 for determining the use state of a redundancy memory for a memory having a redundancy memory part 12b to save a defective memory, and holding means 19 and 11 for holding chip identification information. The determination means is provided with a first output means for receiving an address to output a signal indicating the contents of a first storage means storing the use/non-use of the redundancy memory to a data bus. The holding means is provided with a second output means for receiving a specific address assigned to the address space of the semiconductor memory device and selecting a second storage means storing chip ID information based on the decoding result of the address to output the contents of the selected storage means to the data bus. COPYRIGHT: (C)2006,JPO&NCIPI
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Citations
Patent
Word line selection circuit and row decoder
Hiroyuki Takahashi,Masahiro Yoshida,Noriaki Takeda +2 more
- 04 May 2010
TL;DR: In this paper, a word line selection signal composed of the first voltage and a second voltage higher than the power supply voltage is output not via a level shift circuit according to the address decode signals.
6
Patent
Multi-port memory device with serial input/output interface and control method thereof
Chang-Ho Do
- 29 Dec 2006
TL;DR: A semiconductor memory device includes plural ports for transmitting an input data serial-interfaced with an external device into a global data bus, plural banks for parallel-interfacing with the plural ports through the global data bank, and a mode register set for determining one of a data access mode and a test mode based on the input signal inputted through the Global Data Bus as discussed by the authors.
5
Patent
Semiconductor integtrated circuit including test pads
Dong Uk Lee
- 29 Jan 2014
TL;DR: In this paper, an error detection block is used to determine whether the internal data and the temporary storage data are the same and output a result through one test pad of the port.
4
Patent
Self-addressed subarray precharge
Kim C. Hardee
- 23 Feb 2005
TL;DR: In this paper, the row decoders for subarrays in a memory bank that were previously activated are precharged in response to a bank precharge command, and additional circuitry includes a latch that is set when an array select signal is asserted, and reset when a precharge operation for that bank occurs.
3
Patent
Semiconductor memory device and operating method thereof
Ok Sung Hwa
- 10 May 2018
TL;DR: In this article, the authors present a method of operating a semiconductor memory device comprising a plurality of memory cells using an optimum reference voltage for an input buffer according to the present technique, which includes at least one input buffer for receiving data to be stored in the memory cells, and a reference voltage control part which sets any one of a pre-generated internal voltages having different voltage levels according to a control signal received from a controller for controlling the memory device.
3
References
Patent
Semiconductor memory device with row access in selected column block
Takaaki Suzuki,Shinya Fujioka +1 more
- 05 Mar 1998
TL;DR: In this paper, a hierarchical word-decoders are employed for word selection in a semiconductor memory device with sub-word lines provided for each of column blocks, and a control circuit selects one of the column blocks corresponding to a currently accessed column address in a first case where a row address is different from a successively accessed row address.
25
Patent
Semiconductor memory device used as a digital buffer and reading and writing method thereof
Hiizu Okubo,Hideyuki Aota +1 more
- 14 Jul 1994
TL;DR: In this paper, a semiconductor memory device has memory unit comprising memory cells arranged in a matrix comprising n rows and m columns, where m≧2 and n≧1, each of the memory cells having a single port and being capable of storing a single word of data comprising at least one bit.
14
Patent
Semiconductor memory having both a refresh operation cycle and a normal operation cycle and employing an address non-multiplex system
Yasushi Takahashi,Takashi Shinoda,Masamichi Ishihara,Tetsu Udagawa,Kazumasa Yanagisawa +4 more
- 31 Oct 1997
TL;DR: In this paper, an ordinary read/write operation (normal operation) and a refresh operation (refresh operation) are separated from one another and the number of read amplification circuits is made smaller than that during the refresh operation.
12
Patent
Semiconductor memory device and a reading method thereof
Jin-Young Lee
- 18 Mar 1998
TL;DR: In this article, a column detecting circuit is used to generate DETIO and DETIOB signals, which can be sensed as valid data by external circuitry by disabling a block selecting circuit and disabling a sensing control signal generating circuit.
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