Patent
Semiconductor memory and system
Masaki Aoki
- 22 Sep 2011
30
TL;DR: In this article, a real memory cell including a selection transistor and a resistance variable element which are connected in series between a first voltage line and a second voltage line through a connection node is described.
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Abstract: A semiconductor memory includes a real memory cell including a selection transistor and a resistance variable element which are connected in series between a first voltage line and a second voltage line through a connection node, a real amplification transistor having a gate connected to the connection node, a source connected to a reference voltage line, and a drain connected to a real read line, and a sense amplifier to determine a logic held in the real memory cell by receiving a voltage of the real read line varied with a voltage generated in the connection node by resistance dividing between a source/drain resistance of the selection transistor, and the resistance variable element, the selection transistor receiving a read control voltage at the gate thereof.
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Citations
Patent
Methods for fabricating resistive memory device switching material using ion implantation
Harry Yue Gee,Steven Maxwell,Natividad Vasquez,Mark H. Clark +3 more
- 14 Mar 2014
TL;DR: In this paper, a memory device comprising a doped conductive polycrystalline layer having an electrically resistive portion, is described, which can include resistive switching properties facilitating digital information storage.
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Apparatuses, circuits, and methods for biasing signal lines
Marco-Domenico Tiburzi,Giulio-Giuseppe Marotta +1 more
- 12 Oct 2012
TL;DR: In this paper, the authors describe a memory array with a signal line coupled to a plurality of memory cells and is configured to provide access to the memory cells responsive to a biasing condition of the signal line.
4
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Two transistor ternary random access memory
Simon Peter Tsaoussis
- 29 Sep 2014
TL;DR: In this paper, a two transistor ternary random access memory (TTTRAM) circuit was proposed, where the first transistor has a first emitter, a first collector connected to the input/output switch, and a first base.
1
Patent
Resistive memory device and fabrication methods
Sung Hyun Jo,Kuk-Hwan Kim,Tanmay Kumar +2 more
- 14 Jan 2015
TL;DR: In this paper, a method for forming a resistive memory device includes providing a substrate comprising a first metal material, forming a conductive silicon-bearing layer on top of the first metal, wherein the conductive layer comprises an upper region and a lower region.
1
Patent
Resistive random access memory unit based on resistance voltage division reading
Chunmeng Dou,Liu Jing,Liu Qi,Lyu Hangbing,Liu Ming +4 more
- 03 Apr 2020
TL;DR: In this article, a resistive random access memory unit based on resistance voltage division reading is proposed. But the unit is not suitable for high and low-resistance states, and the voltage change signal of the voltage division point at the gate of the second transistor is not amplified.
1
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Shinichi Yasuda,Keiko Abe,Fujita Shinobu +2 more
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TL;DR: In this article, a semiconductor integrated circuit includes a first resistive change element, a second resistive-change element and a first switching element, each of which is connected to a second power source.
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Hsu Kai Yang
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TL;DR: In this paper, a gate voltage boosting circuit was proposed to prevent a programming current reduction through an MTJ device of a spin-torque MRAM cell array, which is composed of spintorqueMRAM cells that include a MTJ element and a select switching device.
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Patent
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Shinichi Yasuda
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TL;DR: In this article, a memory element consisting of a MIS transistor, a two-terminal variable resistor element, and a fixed resistor element is described, which stores data as a resistance difference.
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Patent
Ultimate magnetic random access memory-based ternary cam
Virgile Javerliac,Mourad El Baraji +1 more
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TL;DR: In this paper, a magnetic random access memory based ternary content addressable memory cell, comprising a first and second magnetic tunnel junction respectively connected to a first-and second straps extending on each side of the first/second magnetic tunnel junctions, respectively, was presented, which can be used in memory devices having a high cell density array.
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