Semiconductor integrated circuit device

TL;DR: In this article, a phase comparator is used to compare the phases of the received clock signals to generate a phase difference signal at a rising timing of the clock signal(CLK).

Abstract: PURPOSE: A semiconductor integrated circuit device is provided to prevent an increase of a chip area, and to generate a clock signal, whose phase is exactly biased by 180 De, and an inverted clock signal. CONSTITUTION: A semiconductor integrated circuit device comprises input buffers(20,22)which receive external clock signals(/CLK,CLK) of mutually inverted phases. A phase comparator(44) receives the external clock signal(CLK) from the input buffer(22) and a delayed version of the external clock signal(CLK) through a delay circuit(40), a dummy output buffer(42) and a dummy input buffer(46). The phase comparator(44) compares the phases of the received clock signals to generate a phase difference signal at a rising timing of the clock signal(CLK). A delay control circuit(48) generates an m-bit delay control signal in response to the phase difference signal, and controls a delay amount of a delay circuit(40). A gate circuit(34) receives the delay control signal, and is controlled by a gate control circuit(32). A latch circuit(36) latches the delay control signal from the gate circuit(34), and outputs the latched control signal to a delay circuit(30), whose delay amount is controlled by the delay control signal from the latch circuit(36). An output buffer(50) receives clock signals(CLK,/CLK) of mutually inverted phases delayed by the delay circuits(30,40).