Register synthesis for speculative computation
Dirk Herrmann,Rolf Ernst +1 more
- 17 Mar 1997
- pp 463-467
TL;DR: This paper presents a register synthesis and allocation technique for speculative computation with branch prediction which is based on life time trees and creates shift register structures with little register and control overhead.
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Abstract: Speculative computation and branch prediction have been used in high-performance processor design for many years. Recently, it has also been applied to high-level synthesis where a priori knowledge of possible control paths provides an even higher performance potential. One problem of speculative techniques is the circuit overhead necessary for correctness preservation. While in processors, overhead is high due to the required generality, high-level synthesis can, again, employ a priori knowledge. The paper presents a register synthesis and allocation technique for speculative computation with branch prediction which is based on life time trees. It creates shift register structures with little register and control overhead.
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Citations
Incorporating speculative execution into scheduling of control-flow intensive behavioral descriptions
Ganesh Lakshminarayana,Anand Raghunathan,Niraj K. Jha +2 more
- 01 May 1998
TL;DR: Experimental results on several benchmarks show that the speculative scheduling algorithm can result in significant (up to seven-fold) improvements in performance as compared to scheduling without speculative execution.
41
Incorporating speculative execution into scheduling of control-flow-intensive designs
TL;DR: This paper presents techniques to incorporate speculative execution in a fine-grained manner into scheduling of control-flow-intensive behavioral descriptions, and shows that the speculative scheduling algorithm can result in significant improvements in performance as compared to scheduling without speculative execution.
32
Toward Speculative Loop Pipelining for High-Level Synthesis
TL;DR: This work proposes a technique for speculative LP that handles both control-flow and memory speculations in a unified manner, allowing a seamless integration to development flows using HLS.
Dynamic branch prediction for high-level synthesis
Vianney Lapotre,Philippe Coussy,Cyrille Chavet,Hugues Nono Wouafo,Robin Danilo +4 more
- 24 Oct 2013
TL;DR: This paper presents a synthesis flow that combines dynamic branch prediction and operation speculation to remove performance bottlenecks imposed by the control flow of applications.
7
References
•Book
Computer Architecture: A Quantitative Approach
John L. Hennessy,David A. Patterson +1 more
- 01 Dec 1989
TL;DR: This best-selling title, considered for over a decade to be essential reading for every serious student and practitioner of computer design, has been updated throughout to address the most important trends facing computer designers today.
12.6K
Global scheduling independent of control dependencies based on condition vectors
Kazutoshi Wakabayashi,H. Tanaka +1 more
- 01 Jul 1992
TL;DR: An algorithm is proposed which generates a single finite state machine controller from parallel individual control sequences derived in the global parallelization process, which can parallelize multiple nests of conditional branches and optimize across the boundaries of basic blocks.
Combining MBP-speculative computation and loop pipelining in high-level synthesis
U. Holtmann,Rolf Ernst +1 more
- 06 Mar 1995
TL;DR: This paper combines MBP-SC and loop pipelining and gives a scheduling algorithm and the results show a considerable speedup compared to previous approaches.
25
Speculative computation for coprocessor synthesis
U. Holtmann,R. Ernst +1 more
- 03 Oct 1993
TL;DR: Speculative computation based on multiple branch prediction is a systematic approach that overcomes the problem of control dependencies and enables wide parallelism.
6
Register estimation from behavioral specifications
A. Sharma,R. Jain +1 more
- 10 Oct 1994
TL;DR: This work determines a lower-bound on the storage area required for executing the data flow graph while satisfying the performance constraint and produces solutions which are very close to the optimal.
5