Open Access
Register Allocation via Weighted Graph Coloring (Technical Summary)
Russell W. Quong,Shu-Ching Chen +1 more
- 01 Jan 1993
TL;DR: It is shown that a WIG gives better allocations than a traditional interference graph when it matters most, namely when there are not enough registers, which is ideal when near-optimal register allocation is desired and spill code is unavoidable.
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Abstract: Register allocation by coloring an interference graph is a common technique. We introduce the weighted interference graph (WIG) which improves upon previous approaches in the following ways: (i) the cost of a coloring accurately models the cost of the register assignment, (ii) arbitrary register spills are handled naturally, as the coloring implicitly determines when and what registers to spill, and (iii) the allocation granularity is freely scalable from an instruction level to a per variable level. In particular, at any granularity, a WIG models the degree of interference between two vertices, which improves upon the traditional interference graph. The weights in a WIG incorporate usage counts to reflect the relative cost for spilling a quantity. We model the savings from keeping a variable in a register via negative edge weights. Our method is ideal when near-optimal register allocation is desired and spill code is unavoidable, such as for large frequently-executed basic blocks, as might be produced by inlining and loop unrolling. We show that a WIG gives better allocations than a traditional interference graph when it matters most, namely when there are not enough registers.
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Citations
On Memory Reuse Between Inputs and Outputs of Dataflow Actors
TL;DR: A new technique to minimize the memory footprints of Digital Signal Processing applications specified with Synchronous Dataflow (SDF) graphs and implemented on shared-memory Multiprocessor System-on-Chip (MPSoCs) is introduced.
20
•Dissertation
Memory Study and Dataflow Representations for Rapid Prototyping of Signal Processing Applications on MPSoCs
Karol Desnos
- 26 Sep 2014
TL;DR: A complete method to study the important aspect of memory characteristic of a DSP application modeled with a dataflow graph is proposed and a new dataflow meta-model is introduced to address the important challenge of managing dynamics in DSP-oriented representations.
Integrated Crossover Based Evolutionary Algorithm for Coloring Vertex-Weighted Graphs
Betul Boz,Gizem Sungu +1 more
TL;DR: This study proposes a novel evolutionary algorithm called Integrated Crossover Based Evolutionary Algorithm with its unique crossover operator and local search technique for coloring vertex-weighted graphs that finds the best number of colors in 70 out of 73 graphs.
Patent
Conflict-free register allocation
Anjul Patney,William J. Dally +1 more
- 07 Jul 2010
TL;DR: In this article, a technique for using a multi-bank register file that reduces the size of or eliminates a switch and/or staging registers that are used to gather input operands for instructions is presented.
6
BitEA: BitVertex Evolutionary Algorithm to Enhance Performance for Register Allocation
Gizem Sungu,Enes Abdulhalik,Alp Arslan Bayrakci,Betül Boz +3 more
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Register allocation & spilling via graph coloring
TL;DR: In a previous paper as mentioned in this paper, we reported the successful use of graph coloring techniques for doing global register allocation in an experimental PL/I optimizing compiler, when the compiler cannot color the...
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