Patent
Refresh controller and memory device including the same
Jong-Min Oh,Ho-young Song +1 more
- 12 Sep 2016
21
TL;DR: In this paper, a refresh controller of a memory device may include a timing controller, a refresh counter and an address generator, and the timing controller generates a counter refresh signal in response to receiving a refresh command provided from an external device, and generates a hammer refresh signal periodically.
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Abstract: A refresh controller of a memory device may include a timing controller, a refresh counter and an address generator. The timing controller generates a counter refresh signal in response to receiving a refresh command provided from an external device, and generates a hammer refresh signal that is activated periodically. The refresh counter generates a counter refresh address signal in response to the counter refresh signal, such that the counter refresh address signal represents a row address, the refresh counter being configured sequentially change the counter refresh address signal. The address generator generates a hammer refresh address signal in response to the hammer refresh signal, the hammer refresh address signal representing an address of a row of the memory device that is physically adjacent to a row of the memory device corresponding to a hammer address that is accessed intensively.
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Citations
Patent
Per row activation count values embedded in storage cell array storage cells
Nale William
- 28 Feb 2019
TL;DR: In this paper, a DRAM memory with a storage cell array is described, where rows and columns are associated with reserved storage cells to store count values that individually count activations of each of the rows.
2
Patent
Semiconductor device having cam that stores address signals
Honoka Enomoto,Masaru Morohashi +1 more
- 19 Mar 2019
TL;DR: In this article, an apparatus may include multiple address registers each storing an address signal and multiple counter-circuits each storing a count value corresponding to an associated one of the address registers.
2
Patent
Memory device and data refreshing method thereof
Nakaoka Yuji
- 01 Jan 2019
TL;DR: In this article, a memory device and a data refreshing method for automatic refresh word line addresses and row hammer refresh line addresses are provided. But the memory cells corresponding to the automatic refresh words line address are not refreshed.
2
Patent
Apparatuses and methods for distributed targeted refresh operations
Noguchi Hidekazu
- 02 Jul 2020
TL;DR: In this article, a memory device may perform auto-refresh operations, as well as one or more types of targeted refresh operations, where particular rows are targeted for a refresh.
1
Patent
Semiconductor memory device capable of performing a hammer refresh operation while performing a normal refresh operation and memory system having the same
Hoon Shin,Do-Yeon Kim,Ho-young Song +2 more
- 09 Aug 2018
TL;DR: In this article, a memory system with a memory cell array and a refresh controller is described, where the memory cell arrays are configured to perform a normal refresh operation and a hammer refresh operation.
1
References
Patent
Row hammer refresh command
Kuljit S. Bains,John B. Halbert,Christopher P. Mozak,Theodore Z. Schoenborn,Zvika Greenfield +4 more
- 31 Oct 2013
TL;DR: In this paper, the memory controller receives an indication of a row hammer event, identifies the row associated with the row hammer events, and sends one or more commands to the memory device to cause the device to perform a targeted refresh that will refresh the victim row.
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Patent
Memory device, memory controller and memory system
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TL;DR: An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionalally arrayed data are provided in this article, where the memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality-of input/output terminals; and an input-output unit provided between the memory cell arrays and the plurality of input/Output terminals.
109
Patent
DRAM with total self refresh and control circuit
Paul S. Lazar,Seung Cheol Oh +1 more
- 18 Jun 2002
TL;DR: In this article, an arbitration and selection circuit that receives a refresh request input signal from an independent oscillator and a row access select RAS input signal is used to schedule either refresh cycles and/or read/write access cycles.
89
Patent
Row hammer monitoring based on stored row hammer threshold value
Kuljit S. Bains,John B. Halbert +1 more
- 28 Jun 2013
TL;DR: In this article, the detection logic of a memory subsystem obtains a threshold for a memory device that indicates a number of accesses within a time window that causes risk of data corruption on a physically adjacent row.
86
Patent
Memory circuits, systems, and modules for performing DRAM refresh operations and methods of operating the same
Chul-Woo Park,Young-Hyun Jun,Joo-Sun Choi,Hongsun Hwang +3 more
- 20 Sep 2011
TL;DR: In this article, a memory module can include a plurality of dynamic memory devices, each of which includes a dynamic memory cell array with respective regions, where the plurality of devices can be configured to operate the respective regions responsive to a command.
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