Patent
Processor system, bus controlling method, and semiconductor device
Keisuke Kaneko,Takao Yamamoto,Masayuki Yamasaki,Nobuo Higaki,Kazushi Kurata,Ryuta Nakanishi +5 more
- 24 Apr 2008
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TL;DR: In this paper, a simply structured multiprocessor system which equally distributes access performance for accessing a shared memory among plural master units accessing the shared memory is presented. But the authors do not consider the case where one of the master units consecutively issues plural access requests without an interval of a predetermined time period, the bus IF unit 4 - 10 restricts the number of consecutive transfer phase executions corresponding to the plural access request to not more than N.
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Abstract: Provided is a simply structured multiprocessor system which equally distributes access performance for accessing a shared memory among plural master units accessing the shared memory. The multiprocessor system includes plural master units PU 0 and PU 1 each of which issues an access request for accessing the shared memory, a bus IF unit 4 - 10 which accesses a bus by a split transaction scheme and separately executes a request phase for accepting the access request; and a transfer phase for executing data transfer in response to the accepted access request. In the case where one of the master units consecutively issues plural access requests without an interval of a predetermined time period, the bus IF unit 4 - 10 restricts the number of consecutive transfer phase executions corresponding to the plural access requests to be not more than N.
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Citations
Patent
Bus control device
Tomoki Ishii,Takao Yamaguchi,Atsushi Yoshida +2 more
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TL;DR: In this paper, a bus controller that can eliminate non-uniformity in data flow rate between links and is arranged between a bus master and a networked communication bus to control the transmission route of a packet flowing through the bus is presented.
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- 16 Mar 2015
TL;DR: In this article, the authors describe a configuration with a core configurable between a single thread (ST) mode and a multithreading (MT) mode, where the primary thread or one of the one or more secondary threads is accessed in the MT mode using an expanded address value, where a core address value concatenated with a thread address value.
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Jonathan D. Bradbury,Fadi Y. Busaba,Mark S. Farrell,Charles W. Gainey,Dan F. Greiner,Heller Lisa,Christian Jacobi,Jeffrey P. Kubala,Damian L. Osisek,Donald W. Schmidt,Slegel Timothy +10 more
- 19 Mar 2015
TL;DR: In this article, the authors propose a dynamic enablement of multithreading in a computer system with a core configurable between a single thread (ST) mode and a multi-thread (MT) mode.
11
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Jane H. Bartik,Jonathan D. Bradbury,Gary M. King,Daniel V. Rosa,Donald W. Schmidt +4 more
- 17 Mar 2015
TL;DR: In this article, the authors present an approach for tracking utilization in a multithreading (MT) computer system, where a core is configured to perform a method that includes resetting a plurality of utilization counters.
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Decentralized allocation of resources and interconnect structures to support the execution of instruction sequences by a plurality of engines
Mohammad Abdallah
- 18 May 2012
TL;DR: In this paper, the authors propose a decentralized resource allocation in an integrated circuit, where the resources are spread across the plurality of engines and are accessed via a global interconnect structure, and the number of requests for access to each resource is compared against a threshold limiter.
7
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