Patent
Prefetching tracks using multiple caches
Michael T. Benhase,Binny S. Gill,Lokesh M. Gupta,James Lee Hafner +3 more
- 22 Jul 2011
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TL;DR: In this paper, a prefetch request indicates prefetch tracks in the sequential access storage medium to read from the non-volatile storage medium and the accessed prefetch track are cached in a nonvolatile memory device.
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Abstract: Provided are a computer program product, sequential access storage device, and method for managing data in a sequential access storage device receiving read requests and write requests from a system with respect to tracks stored in a sequential access storage medium. A prefetch request indicates prefetch tracks in the sequential access storage medium to read from the sequential access storage medium. The accessed prefetch tracks are cached in a non-volatile storage device integrated with the sequential access storage device, wherein the non-volatile storage device is a faster access device than the sequential access storage medium. A read request is received for the prefetch tracks following the caching of the prefetch tracks, wherein the prefetch request is designated to be processed at a lower priority than the read request with respect to the sequential access storage medium. The prefetch tracks are returned from the non-volatile storage device to the read request.
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Citations
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Ash Kevin J,Lokesh M. Gupta,David B. Whitworth,Boyan Zhao +3 more
- 03 Oct 2014
TL;DR: In this article, a multi-level queue-based approach for increased cache performance using multilevel queues by a processor device is described, which includes distributing to each one of a plurality of central processing units (CPUs) workload operations for creating complete tracks from partial tracks, creating sub-queues of the complete tracks, and creating demote scan tasks based on workload of the CPUs.
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TL;DR: In this article, a pre-fetch accelerator circuit is proposed to pre-fetch data from the memory through the memory controller and return the target data to the interface circuit.
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A method and device for improved advanced microcontroller bus architecture (amba) and advanced extensible interface (axi) operations
Arkadi Avrukin,Seungyoon Song,Milan Shah,Thomas Zou +3 more
- 12 May 2017
TL;DR: An Advanced Microcontroller Bus Architecture (AMBA)/Advanced eXtensible Interface (AXI) compatible device and corresponding method capable of efficient reordering of responses from a last level cache (LLC) and/or dynamic random access memory (DRAM) can be found in this paper.
1
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