Proceedings Article10.1109/ASPDAC.1998.669548
Power reduction in pipelines
Sri Parameswaran,Hui Guo +1 more
- 10 Feb 1998
- pp 545-550
TL;DR: A multi-voltage supply scheme is proposed, in which differing behaviours are supplied with differing voltages, and the formulas for computing the supply voltage of each behaviour and minimal power consumption are derived.
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Abstract: The reduction of power consumption for a system level pipeline is addressed in this paper. The pipeline is composed of several stages. Each stage has several behaviours. Different behaviours have differing execution times. The speed of the pipeline is only affected by the behaviours on the critical path of the slowest stages. Other behaviours can be slowed down to decrease the power consumed in the system. We propose a multi-voltage supply scheme, in which differing behaviours are supplied with differing voltages. The formulas for computing the supply voltage of each behaviour and minimal power consumption are derived in this paper. The results of computer experiment show that up to 80% hardware power can be saved with this scheme.
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Citations
Voltage reduction of application-specific heterogeneous multiprocessor systems for power minimisation
Allan Rae,Sri Parameswaran +1 more
- 28 Jan 2000
TL;DR: This power reduction scheme can be used with a randomised search such as a genetic algorithm where multiple trial solutions are tested and the scheme is applied to each trial solution after allocation and scheduling have been performed.
A Structural Customization Approach for Low Power Embedded Systems Design
Hui Guo
- 18 Dec 2010
TL;DR: A structural customization approach, targeting two basic design structures for a multiple choice function that is common in an embedded system: tree structure and chain structure, finds that the chain structure has a lower area cost and offers more customization opportunities, for improving performance and power efficiency, than the tree structure.
4
•Journal Article
Voltage reduction of application-specific heterogeneous multiprocessor systems for power minimisation
Allan Rae,Sri Parameswaran +1 more
TL;DR: In this paper, the authors present a design strategy to reduce power demands in application-specific, heterogeneous multiprocessor systems with interdependent subtasks using a randomised search such as a genetic algorithm where multiple trial solutions are tested.
4
Voltage reduction of application-specific heterogeneous multiprocessor systems for power minimisation
Allan Rae,Sri Parameswaran +1 more
- 09 Jun 2000
TL;DR: In this article, the authors present a design strategy to reduce power demands in application-specific heterogeneous multiprocessor systems with interdependent subtasks, which can be used with a randomised search such as a GA where multiple trial solutions are tested.
2
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Low-power CMOS digital design
TL;DR: In this paper, techniques for low power operation are presented which use the lowest possible supply voltage coupled with architectural, logic style, circuit, and technology optimizations to reduce power consumption in CMOS digital circuits while maintaining computational throughput.
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TL;DR: A review of the power estimation techniques that have recently been proposed for very large scale integrated (VLSI) circuits is presented.
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Optimizing power using transformations
TL;DR: The results indicate that more than an order of magnitude reduction in power can be achieved over current-day design methodologies while maintaining the system throughput; in some cases this can be accomplished while preserving or reducing the implementation area.
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TL;DR: The combination of supply scaling and self-timed circuitry which has some unique advantages, and the thorough analysis of the power savings that are possible using this technique are described.