Proceedings Article10.1109/ISMVL.2003.1201407
Multiple-valued dynamic source-coupled logic
Takahiro Hanyu,Akira Mochizuki,Michitaka Kameyama +2 more
- 16 May 2003
- pp 207-212
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TL;DR: A new multiple-valued current-mode (MVCM) integrated circuit based on dynamic source-coupled logic (SCL) is proposed for low-power VLSI applications and the use of a precharge-evaluate logic style makes steady current flow cut off, thereby greatly saving the power dissipation.
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Abstract: A new multiple-valued current-mode (MVCM) integrated circuit based on dynamic source-coupled logic (SCL) is proposed for low-power VLSI applications. The use of a precharge-evaluate logic style makes steady current flow cut off, thereby greatly saving the power dissipation. A combination of SCL and dynamic logic styles makes it possible to reduce the power dissipation while maintaining a highspeed switching capability due to small input-voltage swing with SCL. As a typical example of a high-performance arithmetic circuit, a radix-2 signed-digit adder based on the proposed dynamic SCL is implemented in a 0.18-/spl mu/m CMOS technology. Its power dissipation is reduced to about 33 percent in comparison with that of the corresponding binary CMOS implementation under the normalized switching delay.
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Citations
Multiple-valued source-coupled logic VLSI based on adaptive threshold control and its applications
H.M. Munirul,Michitaka Kameyama +1 more
- 19 May 2004
TL;DR: A new multiple-valued current-mode (MVCM) integrated circuit, based on adaptive threshold voltage control (ATVC) is proposed for high-speed VLSI applications, while maintaining low power.
2
A new multi-valued current-mode adder based on negative-differential resistance using ULP diodes
Ilham Hassoune,Alexander Drummond,Arnaud Gaudissart,David Bol,David Levacq,Denis Flandre,Jean Didier Legat +6 more
TL;DR: The concept of the negative impedance region of the ULP (ultra-low power) diode is exploited to design a signed-digit full-adder (SDFA), which has no carry propagation which means that addition can be made in constant time and become more competitive for increasing word lengths.
2
High-Performance Multiple-Valued Comparator Based on Active-Load Dual-Rail Differential Logic for Crosstalk-Noise Reduction
Akira Mochizuki,M. Miura,Takahiro Hanyu +2 more
- 13 May 2007
TL;DR: It is demonstrated in 0.18 mum CMOS that the noise-reduction ratio and the switching delay of the proposed comparator is superior to those of a corresponding previous one.
2
Signed-digit CMOS (SD-CMOS) logic circuits with dynamic operation
H. Fukuda
- 19 May 2004
TL;DR: The proposed CMOS basic circuits utilize a multi-voltage power supply to enable dynamic operation with pre-charged output terminals at signal level 0 (VDD1) and are applicable to arithmetic circuits for highly accurate, high-speed processors.
2
A cell library for low power high performance CMOS voltage-mode quaternary logic
Ricardo Cardoso da Silva,Henri Ivanov Boudinov,Luigi Carro +2 more
- 28 Aug 2006
TL;DR: A new method to implement high performance and low power quaternary circuits using multi-threshold transistors and 3 power supply lines is presented in this work.
1
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TL;DR: A new multiple-valued current-mode MOS integrated circuit is proposed for high-speed arithmetic systems at low supply voltage and the performance is evaluated to be about 1.4 times faster than that of a corresponding binary implementation under the normalized power dissipation.
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•Journal Article
An MOS current mode logic (MCML) circuit for low-power GHz processors
M. Yamashina,H. Yamada +1 more
TL;DR: In this article, a 0.5 μm MOS Current Mode Logic (MCML) circuit was proposed to operate at 1.2 V while maintaining high-speed performance comparable with that of bipolar current mode circuits.
40
Fully source-coupled logic based multiple-valued VLSI
T. Ike,Takahiro Hanyu,Michitaka Kameyama +2 more
- 15 May 2002
TL;DR: A novel source-coupled logic style using multiple-valued signals, which operates with an input voltage swing of about 0.3 V is proposed for high-speed and low-power VLSI systems, and its performance is superior to both corresponding binary static CMOS andmultiple-valued current-mode (MVCM) implementation.
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