Patent
Method to implement a large resettable static RAM without the large surge current
Raymond M. Leong
- 21 Feb 1991
22
TL;DR: In this paper, a resettable SRAM architecture and method that eliminates the need to reset all memory cells in the data memory array and requires only the resetting of one flag bit per block of data.
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Abstract: A resettable SRAM architecture and method that eliminates the need to reset all memory cells in the data memory array and requires only the resetting of one flag bit per block of data. This prevents superfluous activation of access circuits and memory cell transistors, thereby reducing power consumption and parasitic noise.
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Citations
Patent
Semiconductor Integrated Circuit Device
Toshio Sasaki,Kazuki Fukuoka,Ryo Mori,Y. Yasu +3 more
- 09 Nov 2007
TL;DR: In this article, a low-voltage control without largely increasing the circuit layout area in a low power consumption structure is presented. But the authors focus on the case of low-speed control, where the region operates on voltages between a power supply voltage and a virtual reference potential.
127
Patent
Flash eprom with block erase flags for over-erase protection
Tien-Ler Lin,Ray L. Wan,Ling-Wen No. Lane Hsiao,Gilbert Sung +3 more
- 28 May 1993
TL;DR: In this article, a flash memory array is organized into a plurality of blocks of memory cells, and an erase verify circuit is used to separate erasure of blocks in the plurality of block memory cells.
84
Patent
Decoded wordline driver with positive and negative voltage modes
Tom Dang-Hsing Yiu,Teruhiko Kamei,Chun-Hsiung Hung,Ray-Lin Wan,Yao-Wu Cheng +4 more
- 26 Jan 1995
TL;DR: In this paper, an inverting driver (300) has an input (302) which receives a wordline select signal, and an output (301) coupled to the wordline, a first supply voltage input connected to the first-supply voltage selector and second-supplied voltage input connecting to the second-source voltage selector.
38
Patent
Static random access memory circuits
Andy L. Lee
- 27 Jul 1998
TL;DR: A static random access memory (SRAM) as discussed by the authors is a type of memory that is especially suitable for such uses as inclusion on a programmable logic device to provide programmable control of the configuration of that device.
27
Patent
Block-level wordline enablement to reduce negative wordline stress
Tom Dang-Hsing Yiu,I-Long Lee,Kuen-Long Chang,Han-Sung Chen,Tzeng-Huei Shiau,Chun-Hsiung Hung,Ray-Lin Wan +6 more
- 06 Feb 1997
TL;DR: In this article, a block selector circuit is coupled to a voltage circuit and selectively switches each of the local outputs to apply either an erasing voltage or a non-erasing voltage onto the wordlines of the associated block of floating gate memory cells.
23
References
Patent
Content addressable memory with flag storage to indicate memory state
Takeo Nakabayashi,Kondo Harufusa +1 more
- 12 Dec 1988
TL;DR: A content addressable memory device capable of correct retrieval operation comprises a flag bit column (12) provided in a memory cell array as discussed by the authors, which stores a flag signal indicating whether a word is in a data written state or an empty state.
40
Patent
Non-volatile semiconductor memory device capable of being erased and written electrically
Kawamata Noboru
- 16 Feb 1989
TL;DR: In this paper, the enable flag is used to indicate whether the respective data of a first EEPROM cell group 1 is made to be a protection object or not, to protect important data from disappearance.
8
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