Patent
Method and system for providing a single-instruction, multiple-data execution unit for performing single-instruction, multiple-data operations within a superscalar data processing system
Ramesh C. Agarwal,Randall Dean Groves,Fred G. Gustavson,Mark Johnson,Brett Olsson +4 more
- 28 Sep 1994
78
TL;DR: A single-instruction, multiple-data (SIMD) execution unit for use in conjunction with a superscalar data processing system is provided in this article, where a branch execution unit fetches instructions from memory and dispatches vector processing instructions to the SIMD execution unit via the instruction bus.
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Abstract: A single-instruction, multiple-data (SIMD) execution unit for use in conjunction with a superscalar data processing system is provided. The SIMD execution unit is coupled to a branch execution unit within a superscalar processor. The branch execution unit fetches instructions from memory and dispatches vector processing instructions to the SIMD execution unit via the instruction bus. The SIMD execution unit includes a control unit and a plurality of processing elements for performing arithmetic operations. The processing elements further include a register file having multiple registers and an arithmetic logic unit coupled to the register file. The arithmetic logic unit may include a fixed-point unit for performing fixed-point vector calculations and a floating-point unit for performing floating-point vector calculations. Once the control unit within the SIMD execution unit receives a vector instruction, the control unit translates the instruction into commands for execution by selected processing elements within the SIMD execution unit. If such a vector instruction requires access to memory, a fixed point execution unit within the superscalar processor may be utilized to calculate a memory address which is then utilized by the SIMD execution unit to access memory.
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Citations
Patent
Alignment and ordering of vector elements for single instruction multiple data processing
Timothy J. Van Hook,Peter Yan-Tek Hsu,William A. Huffman,Henry Packard Moreton,Earl A. Killian +4 more
- 06 Feb 2007
TL;DR: In this paper, the alignment and ordering of vector elements for SIMD processing is described, and a starting byte specifying the first byte of an aligned vector is determined, and then a vector is extracted from the first register and the second register, and replicated into the elements in the third register in a particular order suitable for subsequent SIMD vector processing.
251
Patent
Programmable processor and method with wide operations
Craig Hansen,John Moussouris,Alexia Massalin +2 more
- 12 Jul 2004
138
Patent
SIMD datapath coupled to scalar/vector/address/conditional data register file with selective subpath scalar processing mode
Michael K. Gschwind,Harm Peter Hofstee,Martin Edward Hopkins +2 more
- 14 Aug 2001
TL;DR: In this paper, a processor designed to operate in a plurality of modes for processing vector and scalar instructions is presented, where register files are each for storing scalar and vector data and address information.
131
Patent
System with wide operand architecture, and method
Craig Hansen
- 24 Aug 1999
TL;DR: In this article, a general purpose processor with four copies of an access unit, with an access instruction fetch queue A-queue (101-104) is coupled to an access register file AR (105-108) which is coupled with two access functional units A (109-116).
130
Patent
Method for providing extended precision in SIMD vector arithmetic operations
Timothy J. Van Hook,Peter Yan-Tek Hsu,William A. Huffman,Henry Packard Moreton,Earl A. Killian +4 more
- 30 Dec 1998
TL;DR: In this article, an extended precision in SIMD arithmetic operations in a processor having a register file and an accumulator is provided. But the present invention is limited to a single-core processor.
105
References
Patent
Adaptive instruction processing by array processor having processor identification and data dependent status registers in each processing element
Hungwen Li,Ching-Chy Wang +1 more
- 10 Mar 1987
TL;DR: In this article, an array processor made up of adaptive processing elements can adapt dynamically to changes in its input data stream, and thus can be dynamically optimized, resulting in greatly enhanced performance at very low incremental cost.
93
Patent
Decoded instruction cache architecture with each instruction field in multiple-instruction cache line directly connected to specific functional unit
Einar Ristad,Bjørn Olav Bakka,Inge Birkeli,Nils Anker Orthe +3 more
- 22 Dec 1993
TL;DR: In this paper, a decoded instruction cache with multiple instructions per cache line is proposed, where the decode logic fills the cache line with instructions up to its limit during run time cache misses, enabling the processor to dispatch multiple instructions during one clock cycle.
74
Patent
A computer architecture for the concurrent execution of sequential programs
Manoj Kumar,Ambuj Goyal +1 more
- 22 May 1990
TL;DR: In this article, a computer system processes mixed control, indexing and data manipulation instructions in groups of N instructions at a time, where data used by the control and indexing instructions is stored in a group of identical memory structures which are accessible by each of the Dispatch Units.
63
Patent
Data processor having a plurality of operating units, logical registers, and physical registers for parallel instructions execution
Tohru Shonai,Eiki Kamada,Shigeo Takeuchi +2 more
- 21 May 1986
TL;DR: In this paper, a logical register group and a physical register group are disposed to execute a plurality of instructions in parallel, and a circuit which supplies an operand data from the physical register groups to each logical operation unit and writes the operation result data of each ALU into the physical group and into the logical group.
48
Patent
Method and System for Single Cycle Dispatch of Multiple Instructions in a Superscalar Processor System
A Curley James,Chin-Cheng Kau,David S Levitan,Aubrey D Ogden,Ali A Poursepanj,Paul Kang-Guo Tu,Donald E Waldecker +6 more
- 27 Dec 1993
TL;DR: In this article, a method and system for permitting single cycle instruction dispatch in a superscalar processor system which dispatches multiple instructions simultaneously to a group of execution units for execution and placement of results thereof within specified general purpose registers is presented.
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