Patent
Memory device and memory system comprising a memory device and a memory control device
Peter Gregorius
- 09 Oct 2008
6
TL;DR: In this article, a memory device comprises a clock generating unit being configured to generate a read clock signal, the clock generator being connected to a first clock signal contact configured to send the read clock signals, and the memory device being configurable to send data signals in a phase and frequency accurate manner.
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Abstract: In an embodiment, a memory device comprises a clock generating unit being configured to generate a read clock signal, the clock generating unit being connected to a first clock signal contact configured to send the read clock signal, and the clock generating unit being connected to data signal contacts being configured to send data signals, the memory device being configured to send the data signals in a phase and frequency accurate (source synchronous) manner with regard to the read clock signal.
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Citations
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Multi channel semiconductor device having multi dies and operation method thereof
Yoon-Joo Eom,Park Joon Young,Bae Yong Cheol,Won Young Lee,Jang Seong Jin,Jung-Hwan Choi,Choi Joo Sun +6 more
- 09 Jul 2015
TL;DR: In this paper, a multi-channel semiconductor device is described, where a substrate, a first die on the substrate and having a first channel to function as a first chip; and a second die on a substrate having a second channel different from the first channel and including the same storage capacity and physical size as the first die.
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TL;DR: In this paper, the first and second dies are disposed in one package, and the package includes an interconnection circuit disposed between the first die and the second die to transfer signals.
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TL;DR: In this paper, a communication system management interface includes a control master and slaves under management by the control master, where each slave has at least an input signal connected to an output signal of another device to form a daisy-chain.
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Eric Lyell Hill,Russell R. Newcomb,Shu-Yi Yu +2 more
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TL;DR: In this paper, a clock training sweep operation is performed to determine phase relationships for two write clocks with respect to a command clock, and a voting tally is maintained during the second sweep operation to record phase agreement at each step.
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High capacity, high performance memory system
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TL;DR: In this article, the memory controller and memory devices are packaged on a single substrate using package-on-package technology, which allows the relayed C/A signals to connect from memory device to memory device using wire bonding.
1
References
Patent
Clock generating circuit
Katsuhiko Takayama
- 18 Aug 2005
TL;DR: In this article, the phase difference between the output signals of the two phase interpolators is measured by a closed loop and formed a ring oscillator circuit, which is then fed back to an input terminal of a delay circuit to construct a closed-loop and form an oscillation output signal.
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Patent
Memory system with two clock lines and a memory device
Hermann Ruckerbauer,Christian Sichert,Dominique Savignac,Peter Gregorius,Paul Wallner +4 more
- 30 Sep 2004
TL;DR: In this article, a memory system with two clock lines is described. But the authors focus on a single memory device and do not consider the synchronization of the clock signals from the memory controller to the memory device.
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